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M
93C56A/B
2K 5.0V Automotive Temperature Microwire® Serial EEPROM
FEATURES
• Single supply 5.0V operation
• Low power CMOS technology
- 1 mA active current (typical)
- 1 µA standby current (maximum)
• 256 x 8 bit organization (93C56A)
• 128 x 16 bit organization (93C56B)
• Self-timed ERASE and WRITE cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE
cycles
• Sequential READ function
• 100,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Available for the following temperature ranges:
- Automotive (E):
-40°C to +125°C
DESCRIPTION
The Microchip Technology Inc. 93C56A/B is a 2K-bit,
low-voltage serial Electrically Erasable PROM. The
device memory is configured as 256 x 8 bits (93C56A)
or 128 x 16 bits (93C56B). Advanced CMOS technol-
ogy makes this device ideal for low-power, nonvolatile
memory applications. The 93C56A/B is available in
standard 8-pin DIP and surface mount SOIC packages.
This device is only recommeded for 5V automotive
temperature applications. For all commercial and
industrial applications, the 93LC56A/B is recom-
mended.
PACKAGE TYPE
PDIP
CS
VCC
1
CLK 2
DI 3
DO 4
8
7 NC
6 NC
5 VSS
SOIC
CS
CLK
DI
DO
1
2
3
4
8 VCC
7 NC
6 NC
5 VSS
BLOCK DIAGRAM
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
COUNTER
DI
CS
CLK
DATA
REGISTER
MEMORY
DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
VCC
VSS
Microwire is a registered trademark of National Semiconductor.
© 1998 Microchip Technology Inc.
Preliminary
DS21206B-page 1

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93C56A/B
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Maximum Ratings*
VCC ...................................................................................7.0V
All inputs and outputs w.r.t. VSS ................ -0.6V to Vcc +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied.................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins................................................4 kV
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-1: PIN FUNCTION TABLE
Name
Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
NC No Connect
VCC Power Supply
TABLE 1-2: DC AND AC ELECTRICAL CHARACTERISTICS
All parameters apply over the Automotive (E)VCC = +4.5V to +5.5VTamb = -40°C to +125°C
specified operating ranges
unless otherwise noted
Parameter
Symbol Min.
Max.
Units
Conditions
High level input voltage
VIH
2.0 VCC +1
V (Note 2)
Low level input voltage
VIL -0.3 0.8
V
Low level output voltage
VOL — 0.4 V IOL = 2.1 mA; VCC = 4.5V
High level output voltage
VOH
2.4
V IOH = -400 µA; VCC = 4.5V
Input leakage current
ILI -10 10 µA VIN = VSS to VCC
Output leakage current
ILO -10 10 µA VOUT = VSS to VCC
Pin capacitance
(all inputs/outputs)
CIN, COUT
7
pF
VIN/VOUT = 0 V (Notes 1 & 2)
Tamb = +25°C, FCLK = 1 MHz
Operating current
ICC write
ICC read
1.5 mA
1 mA
Standby current
ICCS
1
µA CS = VSS
Clock frequency
FCLK
2 MHz
Clock high time
TCKH
250
ns
Clock low time
TCKL
250
ns
Chip select setup time
TCSS
50
ns Relative to CLK
Chip select hold time
TCSH
0
— ns Relative to CLK
Chip select low time
TCSL
250
ns
Data input setup time
TDIS
100
ns Relative to CLK
Data input hold time
TDIH
100
ns Relative to CLK
Data output delay time
TPD — 400 ns CL = 100 pF
Data output disable time
TCZ — 100 ns CL = 100 pF (Note 2)
Status valid time
TSV — 500 ns CL = 100 pF
TWC
2 ms ERASE/WRITE mode
Program cycle time
TEC
6 ms ERAL mode
TWL
15 ms WRAL mode
Endurance
— 100K — cycles 25°C, VCC = 5.0V, Block Mode (Note 3)
Note 1: This parameter is tested at Tamb = 25°C and FCLK = 1 MHz.
2: This parameter is periodically sampled and not 100% tested.
3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which may be obtained on Microchip’s BBS or web-
site.
DS21206B-page 2
Preliminary
© 1998 Microchip Technology Inc.

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93C56A/B
2.0 PIN DESCRIPTION
2.1 Chip Select (CS)
A high level selects the device. A low level deselects
the device and forces it into standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the CS input signal. If CS is
brought low during a program cycle, the device will go
into standby mode as soon as the programming cycle
is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93C56A/B.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
TABLE 2-1: INSTRUCTION SET FOR 93C56A
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detecting a START condition, the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (Table 2-1
and Table 2-2). CLK and DI then become don't care
inputs waiting for a new START condition to be
detected.
Note: CS must go low between consecutive
instructions.
2.3 Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4 Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation
has been initiated. The status signal is not available on
DO, if CS is held low during the entire ERASE or
WRITE cycle. In this case, DO is in the HIGH-Z mode.
If status is checked after the ERASE/WRITE cycle, the
data line will be high to indicate the device is ready.
.
Instruction SB Opcode
Address
Data In Data Out Req. CLK Cycles
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
1
1
1
1
1
1
1
11
X A7 A6 A5 A4 A3 A2 A1 A0
(RDY/BSY)
00 1 0 X X X X X X X —
(RDY/BSY)
00 0 0 X X X X X X X —
HIGH-Z
00 1 1 X X X X X X X —
HIGH-Z
10
X A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0
01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)
00 0 1 X X X X X X X D7 - D0 (RDY/BSY)
12
12
12
12
20
20
20
TABLE 2-2: INSTRUCTION SET FOR 93C56B
Instruction SB Opcode
Address
Data In
ERASE 1
11
X A6 A5 A4 A3 A2 A1 A0
ERAL
1
00
1 0XXXXXX
EWDS 1 00 0 0 X X X X X X —
EWEN 1 00 1 1 X X X X X X —
READ 1
10
X A6 A5 A4 A3 A2 A1 A0
WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0
WRAL 1 00 0 1 X X X X X X D15 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D15 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
11
11
11
11
27
27
27
© 1998 Microchip Technology Inc.
Preliminary
DS21206B-page 4-3