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CAT93C56/57 (Die Rev. E)
2K-Bit Microwire Serial EEPROM
FEATURES
ALOGEN FR
LEA D F REETM
I High speed operation: 1MHz
I Low power CMOS technology
I 1.8 to 6.0 volt operation
I Selectable x8 or x16 memory organization
I Self-timed write cycle with auto-clear
I Hardware and software write protection
I Power-up inadvertant write protection
I 1,000,000 Program/erase cycles
I 100 year data retention
I Commercial, industrial and automotive
temperature ranges
I Sequential read
I “Green” package option available
DESCRIPTION
The CAT93C56/57 are 2K-bit Serial EEPROM memory
devices which are configured as either registers of 16
bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the
DI (or DO) pin. The CAT93C56/57 are manufactured
using Catalyst’s advanced CMOS EEPROM floating
gate technology. The devices are designed to endure
1,000,000 program/erase cycles and has a data reten-
tion of 100 years. The devices are available in 8-pin DIP,
8-pin SOIC, 8-pin TSSOP and 8-pad TDFN packages.
PIN CONFIGURATION
DIP Package (P, L)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
SOIC Package (J,W)
NC
VCC
CS
SK
1
2
3
4
8 ORG
7 GND
6 DO
5 DI
SOIC Package (S,V)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
SOIC Package (K,X)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
TSSOP Package (U,Y)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
TDFN Package (RD4, ZD4)
VCC 8
NC 7
ORG 6
GND 5
1 CS
2 SK
3 DI
4 DO
Bottom View
FUNCTIONAL SYMBOL
VCC
ORG
CS
SK
NC
DI
DO
GND
PIN FUNCTIONS
Pin Name
CS
Function
Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC
GND
+1.8 to 6.0V Power Supply
Ground
ORG
Memory Organization
NC No Connection
Note: When the ORG pin is connected to VCC, the x16 organiza-
tion is selected. When it is connected to ground, the x8 pin is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1088, Rev. M

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CAT93C56/57
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............. -2.0V to +VCC +2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
Stresses above those listed under Absolute Maximum
Ratingsmay cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Typ
Max Units
Cycles/Byte
Years
Volts
mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICC1 Power Supply Current
(Write)
fSK = 1MHz
VCC = 5.0V
ICC2 Power Supply Current
(Read)
fSK = 1MHz
VCC = 5.0V
ISB1 Power Supply Current
(Standby) (x8 Mode)
CS = 0V
ORG=GND
Min Typ Max Units
3 mA
500 µA
10 µA
ISB2 Power Supply Current
(Standby) (x16Mode)
ILI Input Leakage Current
ILO Output Leakage Current
(Including ORG pin)
CS=0V
ORG=Float or VCC
VIN = 0V to VCC
VOUT = 0V to VCC,
CS = 0V
0 10 µA
1 µA
1 µA
VIL1
VIH1
VIL2
VIH2
VOL1
VOH1
VOL2
VOH2
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
4.5V VCC < 5.5V
4.5V VCC < 5.5V
1.8V VCC < 4.5V
1.8V VCC < 4.5V
4.5V VCC < 5.5V
IOL = 2.1mA
4.5V VCC < 5.5V
IOH = -400µA
1.8V VCC < 4.5V
IOL = 1mA
1.8V VCC < 4.5V
IOH = -100µA
-0.1
2
0
VCC x 0.7
2.4
VCC - 0.2
0.8
VCC + 1
VCC x 0.2
VCC+1
0.4
0.2
V
V
V
V
V
V
V
V
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V.
Doc. No. 1088, Rev. M
2

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CAT93C56/57
PIN CAPACITANCE
Symbol
Test
Conditions Min Typ Max Units
COUT(2)
CIN(2)
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
VOUT=0V
VIN=0V
5 pF
5 pF
INSTRUCTION SET
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Device
Type
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
Start
Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Opcode
10
10
11
11
01
01
00
00
00
00
00
00
00
00
Address
x8
A8-A0
A7-A0
A8-A0
A7-A0
A8-A0
A7-A0
x16
A7-A0
A6-A0
A7-A0
A6-A0
A7-A0
A6-A0
11XXXXXXX 11XXXXXX
11XXXXXX 11XXXXX
00XXXXXXX 00XXXXXX
00XXXXXX 00XXXXX
10XXXXXXX 10XXXXXX
10XXXXXX 10XXXXX
01XXXXXXX 01XXXXXX
01XXXXXX 01XXXXX
Data
x8 x16
Comments
Read Address ANA0
Clear Address ANA0
D7-D0
D7-D0
D15-D0 Write Address ANA0
D15-D0
Write Enable
Write Disable
Clear All Addresses
D7-D0 D15-D0 Write All Addresses
D7-D0 D15-D0
A.C. CHARACTERISTICS
Symbol Parameter
Test
Conditions
VCC =
1.8V-6V
Limits
VCC =
2.5V-6V
VCC =
4.5V-5.5V
Min Max Min Max Min Max
Units
tCSS CS Setup Time
200 100
50
ns
tCSH CS Hold Time
00
0
ns
tDIS DI Setup Time
400 200
100
ns
tDIH DI Hold Time
400 200
100
ns
tPD1 Output Delay to 1
1 0.5 0.25 µs
tPD0 Output Delay to 0
CL = 100pF
1
0.5 0.25 µs
tHZ(1)
Output Delay to High-Z
(3)
400 200 100 ns
tEW Program/Erase Pulse Width
10 10 10 ms
tCSMIN
Minimum CS Low Time
1 0.5 0.25
µs
tSKHI
Minimum SK High Time
1 0.5 0.25
µs
tSKLOW Minimum SK Low Time
1 0.5 0.25
µs
tSV Output Delay to Status Valid
1 0.5 0.25 µs
SKMAX Maximum Clock Frequency
DC 250 DC 500 DC 1000 kHz
Note:
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE
and ERASE commands.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
3 Doc. No. 1088, Rev. M