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July 2000
FM93C66
4096-Bit Serial CMOS EEPROM
(MICROWIRE™ Synchronous Bus)
General Description
FM93C66 is a 4096-bit CMOS non-volatile EEPROM organized
as 256 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat-
ible to many of standard Microcontrollers and Microprocessors.
There are 7 instructions implemented on the FM93C66 for various
Read, Write, Erase, and Write Enable/Disable operations. This
device is fabricated using Fairchild Semiconductor floating-gate
CMOS process for high reliability, high endurance and low power
consumption.
“LZ” and “L” versions of FM93C66 offer very low standby current
making them suitable for low power applications. This device is
offered in both SO and TSSOP packages for small space consid-
erations.
Features
I Wide VCC 2.7V - 5.5V
I Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I No Erase instruction required before Write instruction
I Self timed write cycle
I Device status during programming cycles
I 40 year data retention
I Endurance: 1,000,000 data changes
I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Functional Diagram
CS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
REGISTER
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
DECODER
EEPROM ARRAY
16
READ/WRITE AMPS
16
DATA IN/OUT REGISTER
16 BITS
DO DATA OUT BUFFER
VCC
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
VSS
© 2000 Fairchild Semiconductor International
FM93C66 Rev. C.1
1
www.fairchildsemi.com

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Connection Diagram
Dual-In-Line Package (N)
8–Pin SO (M8) and 8–Pin TSSOP (MT8)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 NC
5 GND
Top View
Package Number
N08E, M08A and MTC08
Pin Names
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND
Ground
NC No Connect
VCC Power Supply
NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care
should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation.
Ordering Information
FM 93 C XX LZ E XXX
Letter Description
Package
Temp. Range
Voltage Operating Range
Density
Interface
N
M8
MT8
8-pin DIP
8-pin SO
8-pin TSSOP
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
66 4096 bits
C CMOS
CS Data protect and sequential
read
93 MICROWIRE
Fairchild Memory Prefix
FM93C66 Rev. C.1
2 www.fairchildsemi.com

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Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
ESD rating
-65°C to +150°C
+6.5V to -0.3V
+300°C
2000V
Ambient Operating Temperature
FM93C66
FM93C66E
FM93C66V
Power Supply (VCC)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
4.5V to 5.5V
DC and AC Electrical Characteristics VCC = 4.5V to 5.5V unless otherwise specified
Symbol
ICCA
ICCS
IIL
IOL
VIL
VIH
VOL1
VOH1
VOL2
VOH2
fSK
tSKH
Parameter
Operating Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
Conditions
CS = VIH, SK=1.0 MHz
CS = VIL
VIN = 0V to VCC
(Note 2)
IOL = 2.1 mA
IOH = -400 µA
IOL = 10 µA
IOH = -10 µA
(Note 3)
0°C to +70°C
-40°C to +125°C
Min
-0.1
2
2.4
VCC - 0.2
250
300
Max
1
50
±-1
0.8
VCC +1
0.4
0.2
1
Units
mA
µA
µA
V
V
V
MHz
ns
tSKL SK Low Time
tCS Minimum CS Low Time
tCSS CS Setup Time
tDH DO Hold Time
tDIS DI Setup Time
tCSH CS Hold Time
tDIH DI Hold Time
tPD Output Delay
tSV CS to Status Valid
tDF CS to DO in Hi-Z
tWP Write Cycle Time
(Note 4)
CS = VIL
250 ns
250 ns
50 ns
70 ns
100 ns
0 ns
20 ns
500 ns
500 ns
100 ns
10 ms
FM93C66 Rev. C.1
3 www.fairchildsemi.com

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Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
ESD rating
-65°C to +150°C
+6.5V to -0.3V
+300°C
2000V
Ambient Operating Temperature
FM93C66L/LZ
FM93C66LE/LZE
FM93C66LV/LZV
Power Supply (VCC)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
2.7V to 5.5V
DC and AC Electrical Characteristics VCC = 2.7V to 4.5V unless otherwise specified. Refer to
page 3 for VCC = 4.5V to 5.5V.
Symbol
ICCA
ICCS
Parameter
Operating Current
Standby Current
L
LZ (2.7V to 4.5V)
Conditions
CS = VIH, SK=250 KHz
CS = VIL
Min Max Units
1 mA
10 µA
1 µA
IIL Input Leakage
IOL Output Leakage
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
fSK SK Clock Frequency
tSKH SK High Time
tSKL SK Low Time
tCS Minimum CS Low Time
tCSS CS Setup Time
tDH DO Hold Time
tDIS DI Setup Time
tCSH CS Hold Time
tDIH DI Hold Time
tPD Output Delay
tSV CS to Status Valid
tDF CS to DO in Hi-Z
tWP Write Cycle Time
VIN = 0V to VCC
(Note 2)
IOL = 10µA
IOH = -10µA
(Note 3)
(Note 4)
CS = VIL
-0.1
0.8VCC
0.9VCC
0
1
1
1
0.2
70
0.4
0
0.4
±1
0.15VCC
VCC +1
0.1VCC
250
2
1
0.4
15
µA
V
V
KHz
µs
µs
µs
µs
ns
µs
ns
µs
µs
µs
µs
ms
Capacitance TA = 25°C, f = 1 MHz or
250 KHz (Note 5)
Symbol
COUT
CIN
Test
Output Capacitance
Input Capacitance
Typ Max Units
5 pF
5 pF
AC Test Conditions
Note 1: Stress above those listed under Absolute Maximum Ratingsmay cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2: Typical leakage values are in the 20nA range.
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not
allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 5: This parameter is periodically sampled and not 100% tested.
VCC Range
2.7V VCC 5.5V
(Extended Voltage Levels)
4.5V VCC 5.5V
(TTL Levels)
VIL/VIH
Input Levels
0.3V/1.8V
VIL/VIH
Timing Level
1.0V
VOL/VOH
Timing Level
0.8V/1.5V
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
Output Load: 1 TTL Gate (CL = 100 pF)
IOL/IOH
±10µA
2.1mA/-0.4mA
FM93C66 Rev. C.1
4 www.fairchildsemi.com

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Pin Description
Chip Select (CS)
This is an active high input pin to FM93C66 EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low.
Serial Clock (SK)
This is an input pin to the device and is generated by the master that
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input informa-
tion (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge
of this clock input. This pin is gated by CS signal.
Serial Input (DI)
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input informa-
tion (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
Serial Output (DO)
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Microwire Interface
A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array, a set of 7 instructions are implemented on FM93C66.
The format of each instruction is listed under Table 1.
Instruction
Each of the 7 instructions is explained under individual instruction
descriptions.
Start bit
This is a 1-bit field and is the first bit that is clocked into the device
when a Microwire cycle starts. This bit has to be 1for a valid cycle
to begin. Any number of preceding 0can be clocked into the
device before clocking a 1.
Opcode
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with 2 MSB of address field) select a
particular instruction to be executed.
Address Field
This is an 8-bit field and should immediately follow the Opcode bits.
In FM93C66, all 8 bits are used for address decoding during READ,
WRITE and ERASE instructions. During all other instructions, the
MSB 2 bits are used to decode instruction (along with Opcode bits).
Data Field
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
Table 1. Instruction set
Instruction
READ
WEN
WRITE
WRALL
WDS
ERASE
ERAL
Start Bit Opcode Field
Address Field
Data Field
1 10 A7 A6 A5 A4 A3 A2 A1 A0
1 00 1 1 X X X X X X
1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0
1 00 0 1 X X X X X X D15-D0
1 00 0 0 X X X X X X
1 11 A7 A6 A5 A4 A3 A2 A1 A0
1 00 1 0 X X X X X X
FM93C66 Rev. C.1
5 www.fairchildsemi.com