93CS46.pdf 데이터시트 (총 16 페이지) - 파일 다운로드 93CS46 데이타시트 다운로드

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ST93CS46
ST93CS47
1K (64 x 16) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
READY/BUSY SIGNAL DURING
PROGRAMMING
SINGLE SUPPLY VOLTAGE
www.DataSheet43UV.ctoom5.5V for the ST93CS46
– 2.5V to 5.5V for the ST93CS47
USER DEFINED WRITE PROTECTED AREA
PAGE WRITE MODE (4 WORDS)
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ST93CS46 and ST93CS47 are replaced by
the M93S46
8
1
PSDIP8 (B)
0.4mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST93CS46 and ST93CS47 are 1K bit Electri-
cally Erasable Programmable Memory (EEPROM)
fabricated with SGS-THOMSON’s High Endurance
Single Polysilicon CMOS technology. The memory
is accessed through a serial input D and output Q.
The 1K bit memory is organized as 64 x 16 bit
words.The memory is accessed by a set of instruc-
tions which include Read, Write, Page Write, Write
All and instructions used to set the memory protec-
tion. A Read instruction loads the address of the
first word to be read into an internal address
pointer.
Table 1. Signal Names
S Chip Select Input
D Serial Data Input
Q Serial Data Output
C Serial Clock
PRE
W
Protect Enable
Write Enable
VCC Supply Voltage
VSS Ground
D
C
S
PRE
W
VCC
ST93CS46
ST93CS47
VSS
Q
AI00884B
June 1997
This is information on a product still in production bu t not recommended for new de signs.
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ST93CS46, ST93CS47
Figure 2A. DIP Pin Connections
ST93CS46
ST93CS47
S1
C2
8 VCC
7 PRE
D3
6W
Q4
5 VSS
AI00885B
Figure 2B. SO Pin Connections
ST93CS46
ST93CS47
S1
C2
8 VCC
7 PRE
D3
6W
Q4
5 VSS
AI00886C
www.DataSThaebetl4eU2.c.omAbsolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA Ambient Operating Temperature
–40 to 85
°C
TSTG Storage Temperature
–65 to 150
°C
TLEAD Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
°C
VIO Input or Output Voltages (Q = VOH or Hi-Z)
–0.3 to VCC +0.5
V
VCC Supply Voltage
–0.3 to 6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) (2)
Electrostatic Discharge Voltage (Machine model) (3)
3000
500
V
V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 ).
3. EIAJ IC-121 (Condition C) (200pF, 0 ).
DESCRIPTION (cont’d)
The data is then clocked out serially. The address
pointer is automatically incremented after the data
is output and, if the Chip Select input (S) is held
High, the ST93CS46/47 can output a sequential
stream of data words. In this way, the memory can
be read as a data stream of 16 to 1024 bits, or
continuously as the address counter automatically
rolls over to 00 when the highest address is
reached. Within the time required by a program-
ming cycle (tW), up to 4 words may be written with
the help of the Page Write instruction; the whole
memory may also be erased, or set to a predeter-
mined pattern, by using the Write All instruction.
Within the memory, an user defined area may be
protected against further Write instructions. The
size of this area is defined by the content of a
2/16
Protect Register, located outside of the memory
array. As a final protection step, data may be per-
manently protected by programming a One Time
Programing bit (OTP bit) which locks the Protect
Register content.
Programming is internally self-timed (the external
clock signal on C input may be disconnected or left
running after the start of a Write cycle) and does
not require an erase cycle prior to the Write instruc-
tion. The Write instruction writes 16 bits at one time
into one of the 64 words, the Page Write instruction
writes up to 4 words of 16 bits to sequential loca-
tions, assuming in both cases that all addresses
are outside the Write Protected area.
After the start of the programming cycle, a
Ready/Busy signal is available on the Data output
(Q) when the Chip Select (S) input pin is driven
High.

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ST93CS46, ST93CS47
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
20ns (10% to 90%)
0.4V to 2.4V
Input and Output Timing
Reference Voltages
0.8 and 2V
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Figure 3. AC Testing Input Output Waveforms
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
Table 3. Capacitance (1)
www.DataS(hTeAet=4U2.5co°mC, f = 1 MHz )
Symbol
Parameter
CIN Input Capacitance
COUT
Output Capacitance
Note: 1. Sampled only, not 100% tested.
Test Condition
VIN = 0V
VOUT = 0V
Min
Max
Unit
5 pF
5 pF
Table 4. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V for ST93CS46 and
VCC = 2.5V to 5.5V for ST93CS47)
Symbol
Parameter
Test Condition
Min Max Unit
ILI Input Leakage Current
0V VIN VCC
±2.5 µA
ILO Output Leakage Current
0V VOUT VCC,
Q in Hi-Z
±2.5 µA
ICC Supply Current (TTL Inputs)
S = VIH, f = 1 MHz
3 mA
Supply Current (CMOS Inputs)
S = VIH, f = 1 MHz
2 mA
ICC1 Supply Current (Standby)
S = VSS, C = VSS
50 µA
Input Low Voltage (ST93CS46,47)
4.5V VCC 5.5V
VIL Input Low Voltage (ST93CS46)
3V VCC 5.5V
–0.1
–0.1
0.8
0.2 VCC
V
V
Input Low Voltage (ST93CS47)
2.5V VCC 5.5V
–0.1
0.2 VCC
V
Input High Voltage (ST93CS46,47)
4.5V VCC 5.5V
2
VCC + 1
V
VIH Input High Voltage (ST93CS46)
3V VCC 5.5V
0.8 VCC
VCC + 1
V
Input High Voltage (ST93CS47)
2.5V VCC 5.5V
0.8 VCC
VCC + 1
V
VOL Output Low Voltage
IOL = 2.1mA
IOL = 10 µA
0.4 V
0.2 V
VOH Output High Voltage
IOH = –400µA
IOH = –10µA
2.4
VCC – 0.2
V
V
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ST93CS46, ST93CS47
Table 5. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V for ST93CS46 and
VCC = 2.5V to 5.5V for ST93CS47)
Symbol
Alt
Parameter
Test Condition Min Max Unit
tPRVCH
tWVCH
tSHCH
tPRES
tPES
tCSS
Protect Enable Valid to Clock High
Write Enable Valid to Clock High
Chip Select High to Clock High
50 ns
50 ns
50 ns
tDVCH
tDIS Input Valid to Clock High
100 ns
tCHDX
tDIH Clock High to Input Transition
100 ns
tCHQL
tPD0 Clock High to Output Low
500 ns
tCHQV
tPD1 Clock High to Output Valid
500 ns
tCLPRX
www.DataSheettS4LUW.Xcom
tPREH
tPEH
Clock Low to Protect Enable Transition
Chip Select Low to Write Enable Transition
0 ns
250 ns
tCLSL
tCSH Clock Low to Chip Select Transition
0 ns
tSLSH
tCS Chip Select Low to Chip Select High
Note 1
250
ns
tSHQV
tSV Chip Select High to Output Valid
500 ns
tSLQZ
tDF Chip Select Low to Output Hi-Z
300 ns
tCHCL
tSKH Clock High to Clock Low
Note 2
250
ns
tCLCH
tSKL Clock Low to Clock High
Note 2
250
ns
tW tWP Erase/Write Cycle time
10 ms
fC fSK Clock Frequency
0 1 MHz
Notes: 1. Chip Select must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings tCHCL + tCLCH
must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns.
Figure 4. Synchronous Timing, Start and Op-Code Input
PRE
W
C
S
D
tPRVCH
tWVCH
tCHCL
tSHCH
tCLCH
tDVCH
START
OP CODE
tCHDX
OP CODE
START
OP CODE INPUT
AI00887
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Figure 5. Synchronous Timing, Read or Write
C
S
D
Q
www.DataSheet4U.com
tDVCH
An
Hi-Z
tCHDX
A0
tCHQL
ADDRESS INPUT
ST93CS46, ST93CS47
tCHQV
Q15/Q7
tCLSL
tSLSH
tSLQZ
Q0
DATA OUTPUT
AI00820C
PRE
W
C
S
D
Q
tDVCH
An
Hi-Z
tCHDX
A0/D0
ADDRESS/DATA INPUT
tCLPRX
tSLWX
tCLSL
tSLSH
tSHQV
BUSY
tW
READY
tSLQZ
WRITE CYCLE
AI00888B
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