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93L00
4-Bit Universal Shift Register
General Description
The 93L00 is a 4-bit universal shift register As a high speed
multifunctional sequential logic block it is useful in a wide
variety of register and counter applications It may be used
in serial-serial shift left shift right serial-parallel parallel-
serial and parallel-parallel data register transfers
Features
Y Asynchronous master reset
Y J K inputs to first stage
Connection Diagram
Logic Symbol
Dual-In-Line Package
June 1989
TL F 9576 – 1
Order Number 93L00DMQB or 93L00FMQB
See NS Package Number J16A or W16A
VCC e Pin 16
GND e Pin 8
Pin Names
PE
P0 – P3
J
K
CP
MR
Q0 – Q3
Q3
Description
Parallel Enable Input (Active LOW)
Parallel Inputs
First Stage J Input (Active HIGH)
First Stage K Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Master Reset Input
Parallel Outputs
Complementary Last Stage Output
TL F 9576 – 2
C1995 National Semiconductor Corporation TL F 9576
RRD-B30M105 Printed in U S A

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Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
MIL b65 C to a125 C
Recommended Operating Conditions
Symbol
Parameter
VCC
VIH
VIL
IOH
IOL
TA
ts (H)
ts (L)
th (H)
th (L)
ts (H)
ts (L)
th (H)
th (L)
tw (H)
tw (L)
tw (L)
trec
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Current
Free Air Operating Temperature
Setup Time HIGH or LOW
J K and P0–P3 to CP
Hold Time HIGH or LOW
J K and P0–P3 to CP
Setup Time HIGH or LOW
PE to CP
Hold Time HIGH or LOW
PE to CP
CP Pulse Width
HIGH or LOW
MR Pulse Width LOW
Recovery Time MR to CP
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Min
45
2
b55
60
60
0
0
68
68
0
0
38
38
53
70
93L00 (MIL)
Nom
5
Max
55
07
b0 4
48
125
Units
V
V
V
mA
mA
C
ns
ns
ns
ns
ns
ns
ns
2

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Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
VOH
VOL
II
Input Clamp Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current Max
Input Voltage
VCC e Min II e b10 mA
VCC e Min IOH e Max
VIL e Max VIH e Min
VCC e Min IOL e Max
VIH e Min VIL e Max
VCC e Max VI e 5 5V
24
IIH
High Level Input Current
VCC e Max VI e 2 4V
Inputs
CP
PE
IIL
Low Level Input Current
VCC e Max VI e 0 3V
Inputs
CP
PE
IOS Short Circuit
Output Current
VCC e Max
(Note 2)
b2 5
ICC Supply Current
VCC e Max
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second
Typ
(Note 1)
34
Switching Characteristics
VCC e a5 0V TA e a25 C (See Section 1 for waveforms and load configurations)
93L
Symbol
Parameter
CL e 15 pF
Min Max
fmax
tPLH
tPHL
tPHL
Maximum Shift Frequency
Propagation Delay
CP to Qn
Propagation Delay MR to Qn
10
35
51
60
Max
b1 5
Units
V
V
03 V
1
20
40
46
b400
b800
b920
b25
23
mA
mA
mA
mA
mA
Units
MHz
ns
ns
3

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Functional Description
The Logic Diagrams and Truth Table indicate the functional
characteristics of the 93L00 4-bit shift register The device is
useful in a wide variety of shifting counting and storage
applications It performs serial parallel serial-to-parallel or
parallel-to-serial data transfers
The 93L00 has two primary modes of operation shift right
x(Q0 Q1) and parallel load which are controlled by the
state of the Parallel Enable (PE) input When the PE input is
HIGH serial data enters the first flip-flop Q0 via the J and K
inputs and is shifted one bit in the direction
x x xQ0 Q1 Q2 Q3 following each LOW-to-HIGH
clock transition The JK inputs provide the flexibility of the
JK type input for special applications and the simple D-type
input for general applications by tying the two pins together
Truth Table
Operating
Inputs (MR e H)
Mode
PE J K P0 P1
Shift Mode
H LL X
H LH X
H HL X
H HH X
X
X
X
X
Parallel
L XX L
L
Entry Mode
L
XX
H
H
tna1 e Indicates state after next LOW-to-HIGH clock transition
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
When the PE input is LOW the 93L00 appears as four com-
mon clocked D flip-flops The data on the parallel inputs
P0 – P3 is transferred to the respective Q0 – Q3 outputs fol-
lowing the LOW-to-HIGH clock transition Shift left opera-
xtion (Q3 Q2) can be achieved by tying the Qn outputs to
the Pnb1 inputs and holding the PE input LOW
All serial and parallel data transfers are synchronous occur-
ing after each LOW-to-HIGH clock transition Since the
93L00 utilizes edge triggering there is no restriction on the
activity of the J K Pn and PE inputs for logic operation ex-
cept for the setup and release time requirements A LOW on
the asynchronous Master Reset (MR) input sets all Q out-
puts LOW independent of any other input condition
Outputs tna1
P2 P3 Q0 Q1 Q2 Q3 Q3
X X L Q0 Q1 Q2 Q2
X X Q0 Q0 Q1 Q2 Q2
X X Q0 Q0 Q1 Q2 Q2
X X H Q0 Q1 Q2 Q2
LLL L L LH
HHH H H H L
4

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Logic Diagram
5