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93L08
Dual 4-Bit Latch
General Description
The 93L08 is a dual 4-bit D-type latch designed for general
purpose storage applications in digital systems Each latch
contains both an active LOW Master Reset input and active
LOW Enable inputs
Connection Diagram
Logic Symbol
Dual-In-Line Package
June 1989
TL F 9594 – 1
Order Number 93L08DMQB or 93L08FMQB
See NS Package Number J24A or W24C
VCC e Pin 24
GND e Pin 12
Pin Names
(D0a – D3a
D0b – D3b
E0a E1a E0b E1b
MRa MRb
(Q0a – Q3a
Q0b – Q3b
Description
Parallel Latch Inputs
AND Enable Inputs (Active LOW)
Master Reset Inputs (Active LOW)
Parallel Latch Outputs
TL F 9594 – 2
C1995 National Semiconductor Corporation TL F 9594
RRD-B30M105 Printed in U S A

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Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
MIL b55 C to a125 C
Storage Temperature Range
b65 C to a150 C
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
TA
ts (H)
th (H)
ts (L)
th (L)
tw (L)
tw (L)
trec
Parameter
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
Setup Time HIGH Dn to En
Hold Time HIGH Dn to En
Setup Time LOW Dn to En
Hold Time LOW Dn to En
En Pulse Width LOW
MR Pulse Width LOW
Recovery Time MR to En
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Min
45
2
b55
8
1
18
4
32
30
10
Nom
5
Max
55
07
b400
48
125
Units
V
V
V
mA
mA
C
ns
ns
ns
ns
ns
ns
ns
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
VOH
VOL
II
Input Clamp Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current Max
Input Voltage
VCC e Min II e b10 mA
VCC e Min IOH e Max
VIL e Max VIH e Min
VCC e Min IOL e Max
VIH e Min VIL e Max
VCC e Max VI e 5 5V
24
IIH
High Level Input Current
VCC e Max VI e 2 4V
Inputs
Dn
IIL
Low Level Input Current
VCC e Max VI e 0 3V
Inputs
Dn
IOS Short Circuit
Output Current
VCC e Max (Note 2)
b2 5
ICC Supply Current
VCC e Max (Note 3)
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3 ICC is measured with all outputs open and all inputs grounded
Typ
(Note 1)
Max
b1 5
03
1
20
30
b400
b640
b25
29
Units
V
V
V
mA
mA
mA
mA
mA
2

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Switching Characteristics
VCC e a5 0V TA e a25 C (See Section 3 for waveforms and load configurations)
Symbol
Parameter
CL e 15 pF
Min Max
tPLH
tPHL
tPLH
tPHL
tPHL
Propagation Delay
En to Qn
Propagation Delay
Dn to Qn
Propagation Delay
MR to Qn
45
38
27
29
30
Functional Description
Data can be entered into the latch when both of the enable
inputs are LOW As long as this logic condition exists the
output of the latch will follow the input If either of the enable
inputs goes HIGH the data present in the latch at that time
is held in the latch and is no longer affected by data input
The master reset overrides all other input conditions and
forces the outputs of all the latches LOW when a LOW sig-
nal is applied to the Master Reset input
Truth Table
MR E0 E1 D
H L LL
H L LH
H L HX
H H LX
H H HX
L X XX
Qnb1 e Previous Output State
Qn e Present Output State
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Qn
L
L
Qnb1
Qnb1
Qnb1
L
Units
ns
ns
ns
Operation
Data Entry
Data Entry
Hold
Hold
Hold
Reset
Logic Diagram
TL F 9594 – 3
3

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Physical Dimensions inches (millimeters)
24-Lead Ceramic Dual-In-Line Package (J)
Order Number 93L08DMQB
NS Package Number J24A
24-Lead Ceramic Flat Package (W)
Order Number 93L08FMQB
NS Package Number W24C
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