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June 1989
93L28
Dual 8-Bit Shift Register
General Description
The 93L28 is a high speed serial storage element providing
16 bits of storage in the form of two 8-bit registers The
multifunctional capability of this device is provided by sever-
al features 1) additional gating is provided at the input to
both shift registers so that the input is easily multiplexed
between two sources 2) the clock of each register may be
provided separately or together 3) both the true and com-
plementary outputs are provided from each 8-bit register
and both registers may be master cleared from a common
input
Features
Y 2-input multiplexer provided at data input of each
register
Y Gated clock input circuitry
Y Both true and complementary outputs provided from
last bit of each register
Y Asynchronous master reset common to both registers
Connection Diagram
Dual-In-Line Package
Logic Symbol
TL F 10200 – 1
Order Number 93L28DMQB or 93L28FMQB
See NS Package Number J16A or W16A
VCC e Pin 16
GND e Pin 8
Pin
Names
S
D0 D1
CP
MR
Q7
Q7
Description
Data Select Input
Data Inputs
Clock Pulse Input (Active HIGH)
Common (Pin 9)
Separate (Pins 7 and 10)
Master Reset Input (Active LOW)
Last Stage Output
Complementary Output
TL F 10200 – 2
C1995 National Semiconductor Corporation TL F 10200
RRD-B30M105 Printed in U S A

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Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
MIL b55 C to a125 C
Storage Temperature Range
b65 C to a150 C
Recommended Operating Conditions
Symbol
Parameter
VCC
VIH
VIL
IOH
IOL
TA
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
tw(L)
tw(L)
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
Setup Time HIGH or LOW
Dn to CP
Hold Time HIGH or LOW
Dn to CP
Clock Pulse Width
HIGH or LOW
MR Pulse Width with CP HIGH
MR Pulse Width with CP LOW
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Min
45
2
b55
30
30
0
0
55
55
60
70
93L28 (MIL)
Nom
5
Max
55
07
b400
48
125
Units
V
V
V
mA
mA
C
ns
ns
ns
ns
ns
2

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Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
VOH
VOL
II
Input Clamp Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current Max
Input Voltage
VCC e Min II e b10 mA
VCC e Min IOH e Max
VIL e Max VIH e Min
VCC e Min IOL e Max
VIH e Min VIL e Max
VCC e Max VI e 5 5V
24
IIH HIGH Level
Input Current
VCC e Max VI e 2 4V
MR Dx
CP (7 10)
S
CP Com
IIL LOW Level
Input Current
VCC e Max VI e 0 3V
MR Dx
CP (7 10)
S
CP Com
IOS Short Circuit
Output Current
VCC e Max
(Note 2)
b2 5
ICC Supply Current
VCC e Max
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second
Typ
(Note 1)
Max
b1 5
03
1
20
30
40
60
b400
b600
b800
b1200
b25
25 3
Units
V
V
V
mA
mA
mA
mA
mA
Switching Characteristics
VCC e a5 0V TA e a25 C (See Section 1 for test waveforms and output load)
Symbol
Parameter
CL e 15 pF
Min Max
fmax
tPLH
tPHL
tPHL
Maximum Shift Right Frequency
Propagation Delay
CP to Q7 or Q7
Propagation Delay MR to Q7
50
45
80
110
Units
MHz
ns
ns
3

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Functional Description
The two 8-bit shift registers have a common clock input (pin
9) and separate clock inputs (pins 10 and 7) The clocking
of each register is controlled by the OR function of the sep-
arate and the common clock input Each register is com-
posed of eight clocked RS master slave flip-flops and a
number of gates The clock OR gate drives the eight clock
inputs of the flip-flops in parallel When the two clock inputs
(the separate and the common) to the OR gate are LOW
the slave latches are steady but data can enter the master
latches via the R and S input During the first LOW-to-HIGH
transition of either or both simultaneously of the two clock
inputs the data inputs (R and S) are inhibited so that a later
change in input data will not affect the master then the now
trapped information in the master is transferred to the slave
When the transfer is complete both the master and the
slave are steady as long as either or both clock inputs re-
main HIGH During the HIGH-to-LOW transition of the last
remaining HIGH clock input the transfer path from master
to slave is inhibited first leaving the slave steady in its pres-
ent state The data inputs (R and S) are enabled so that new
data can enter the master Either of the clock inputs can be
used as clock inhibit inputs by applying a logic HIGH signal
Logic Diagram
Each 8-bit shift register has a 2-input multiplexer in front of
the serial data input The two data inputs D0 and D1 are
controlled by the data select input (S) following the Boolean
expression
Serial data in SD e SD0 a SD1
An asynchronous master reset is provided which when acti-
vated by a LOW logic level will clear all 16 stages indepen-
dently of any other input signal
Shift Select Table
Inputs
Output
S D0 D1 Q7 (tna8)
LL
LH
HX
HX
X
X
L
H
L
H
L
H
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
na8 e Indicates state after eight clock pulse
TL F 10200 – 3
4

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Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 93L28DMQB
NS Package Number J16A
5