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June 1989
93L34
8-Bit Addressable Latch
General Description
The 93L34 is an 8-bit addressable latch designed for gener-
al purpose storage applications in digital systems It is a
multifunctional device capable of storing single line data in
eight addressable latches and being a one-of-eight decoder
and demultiplexer with active level HIGH outputs The de-
vice also incorporates an active LOW common clear for re-
setting all latches as well as an active LOW enable
Features
Y Serial to parallel capability
Y Eight bits of storage with output of each bit available
Y Random (addressable) data entry
Y Active high demultiplexing or decoding capability
Y Easily expandable
Y Common conditional clear
Connection Diagram
Dual-In-Line Package
Logic Symbol
TL F 10201 – 1
Order Number 93L34DMQB or 93L34FMQB
See NS Package Number J16A or W16A
VCC e Pin 16
GND e Pin 8
Pin Names
A0 – A3
D
E
CL
Q0 – Q7
Description
Address Inputs
Data Input
Enable Input (Active LOW)
Clear Input (Active LOW)
Parallel Latch Outputs
TL F 10201 – 2
C1995 National Semiconductor Corporation TL F 10201
RRD-B30M105 Printed in U S A

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Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
Military
b55 C to a125 C
Storage Temperature Range
b65 C to a150 C
Recommended Operating Conditions
Symbol
Parameter
VCC
VIH
VIL
IOH
IOL
TA
ts (H)
th (H)
ts (L)
th (L)
ts (H)
ts (L)
tw (L)
tw (L)
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Current
Free Air Operating Temperature
Setup Time HIGH D to E
Hold Time HIGH D to E
Setup Time LOW D to E
Hold Time LOW D to E
Setup Time HIGH or LOW
An to E
E Pulse Width LOW
CL Pulse Width LOW
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Min
45
2
b55
45
b5
45
b7
10
10
26
35
93L34 (Mil)
Nom
5
Max
55
07
b400
48
125
Units
V
V
V
mA
mA
C
ns
ns
ns
ns
ns
ns
ns
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
VOH
VOL
II
Input Clamp Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current Max
Input Voltage
VCC e Min II e b10 mA
VCC e Min IOH e Max
VIL e Max VIH e Min
VCC e Min IOL e Max
VIH e Min VIL e Max
VCC e Max VI e 5 5V
24
IIH
High Level Input Current
VCC e Max VI e 2 4V
Inputs
E
IIL
Low Level Input Current
VCC e Max VI e 0 3V
Inputs
E
IOS Short Circuit
Output Current
VCC e Max (Note 2)
b2 5
ICC Supply Current
VCC e Max (Note 3)
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3 ICC is measured with all outputs open and all inputs grounded
Typ
(Note 1)
Max
b1 5
03
1
20
30
b0 4
b0 6
b25
21
Units
V
V
V
mA
mA
mA
mA
mA
2

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Switching Characteristics VCC e a5 0V TA e a25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
CL e 15 pF
Min Max
Units
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Propagation Delay
E to Qn
Propagation Delay
D to Qn
Propagation Delay
An to Qn
Propagation Delay
CL to Qn
45
42
ns
65
45 ns
66 ns
66
55 ns
Functional Description
The 93L34 has four modes of operation which are shown in
the Mode Select Table In the addressable latch mode data
on the data line (D) is written into the addressed latch The
addressed latch will follow the Data input with all non-ad-
dressed latches remaining in their previous states In the
memory mode all latches remain in their previous state and
are unaffected by the data or address inputs To eliminate
the possibility of entering erroneous data into the latches
the Enable should be held HIGH while the Address lines are
changing In the 1-of-8 decoding or demultiplexing mode
the addressed output will follow the state of the D input with
all other outputs in the LOW state In the clear mode all
outputs are LOW and unaffected by the address and data
inputs When operating the 93L34 as an addressable latch
changing more than one bit of the address could impose a
transient wrong address Therefore this should only be
done while in the memory mode
Mode Select Table
E CL
Mode
L H Addressable Latch
H H Memory
L L Active HIGH 8-Channel Demultiplexer
H L Clear
3

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Truth Table
Inputs
CL E A0 A1
L HX X
L LL L
L
LH
L
L LL H
  
  
L
LH
H
H HX X
H LL L
H LH L
H LL H
  
  
H LH H
H e HIGH Voltage Level
A2 Q0
Q1
XL
LD
LL
LL


HL
L
L
D
L


L
X Qt–1 Qt–1
LD
Qt – 1
L Qt–1 D
L Qt–1 Qt–1




H Qt–1 Qt–1
L e LOW Voltage Level
Outputs
Q2 Q3 Q4 Q5 Q6
LLLLL
LLLLL
LLLLL
DL L L L


LLLLL
Qt–1 Qt – 1 Qt – 1 Qt – 1 Qt – 1
Qt– 1
Qt – 1
D


Qt – 1
Qt – 1
Qt – 1
Qt –1


Qt –1
X e Immaterial
Qt – 1
Qt – 1
Qt –1


Qt –1
Qt – 1
Qt – 1
Qt –1


Qt –1
Qt – 1
Qt – 1
Qt –1


Qt –1
Qt–1 e Previous Output State
Q7
L
L
L
L


L
Qt – 1
Qt – 1
Qt – 1
Qt –1


D
Mode
Clear
Demultiplex
Memory
Addressable
Latch
4

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Logic Diagram
TL F 10201 – 3
5