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M
93LC56A/B
2K 2.5V Microwire® Serial EEPROM
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current (typical)
- 1 µA standby current (maximum)
• 256 x 8 bit organization (93LC56A)
• 128 x 16 bit organization (93LC56B)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC and 8-pin TSSOP packages
• Available for the following temperature ranges:
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
PACKAGE TYPE
DIP
SOIC
BLOCK DIAGRAM
MEMORY
ARRAY
ADDRESS
DECODER
DI
CS
CLK
DATA
REGISTER
ADDRESS
COUNTER
OUTPUT
BUFFER
DO
MODE
DECODE
LOGIC
CLOCK
GENERATOR
Vcc
Vss
DESCRIPTION
The Microchip Technology Inc. 93LC56A/B are 2K-bit,
low-voltage serial Electrically Erasable PROMs. The
device memory is configured as x8 (93LC56A) or
x16 bits (93LC56B). Advanced CMOS technology
makes these devices ideal for low power nonvolatile
memory applications. The 93LC56A/B is available in
standard 8-pin DIP, surface mount SOIC, and TSSOP
packages. The 93LC56AX/BX are only offered in a
150-mil SOIC package.
SOIC
TSSOP
CS 1
CLK 2
DI 3
DO 4
8 Vcc
CS
7 NC
CLK
6 NC
DI
5 Vss
DO
1
2
3
4
8 VCC
NU 1
7 NC
Vcc 2
6 NC
CS 3
5 Vss CLK 4
CS 1
8 NC CLK 2
DI 3
7 Vss
DO 4
6 DO
5 DI
8 Vcc
7 NC
6 NC
5 Vss
Microwire is a registered trademark of National Semiconductor.
© 1997 Microchip Technology Inc.
Preliminary
DS21208A-page 1

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93LC56A/B
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Maximum Ratings*
VCC...................................................................................7.0V
All inputs and outputs w.r.t. Vss ................ -0.6V to Vcc +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied.................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins................................................4 kV
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-1 PIN FUNCTION TABLE
Name
Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
NC No Connect
VCC Power Supply
TABLE 1-2 DC AND AC ELECTRICAL CHARACTERISTICS
All parameters apply over the specified Commercial (C): VCC = +2.5V to +6.0V
operating ranges unless otherwise
Industrial (I):
VCC = +2.5V to +6.0V
noted
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
Parameter
Symbol
Min.
Max.
Units
Conditions
High level input voltage
VIH1
VIH2
2.0
0.7 Vcc
Vcc +1
Vcc +1
V 2.7V VCC 5.5V (Note 2)
V VCC < 2.7V
Low level input voltage
VIL1
-0.3
0.8
V VCC > 2.7V (Note 2)
VIL2 -0.3 0.2 Vcc V VCC < 2.7V
Low level output voltage
VOL1
0.4
V IOL = 2.1 mA; Vcc = 4.5V
VOL2
0.2
V IOL =100 µA; Vcc = Vcc Min.
High level output voltage
VOH1
VOH2
2.4
Vcc-0.2
V IOH = -400 µA; Vcc = 4.5V
V IOH = -100 µA; Vcc = Vcc Min.
Input leakage current
ILI -10 10 µA VIN = VSS
Output leakage current
ILO -10 10 µA VOUT = VSS
Pin capacitance
(all inputs/outputs)
CIN, COUT
7
pF
VIN/VOUT = 0 V (Notes 1 & 2)
Tamb = +25°C, Fclk = 1 MHz
Operating current
ICC read
ICC write
1 mA FCLK = 2 MHz; VCC = 6.0V
500 µA FCLK = 1 MHz; VCC = 3.0V
1.5 mA
Standby current
ICCS
1
µA CS = VSS
Clock frequency
FCLK
2
MHz
VCC > 4.5V
1
MHz
VCC < 4.5V
Clock high time
TCKH
250
ns
Clock low time
TCKL
250
ns
Chip select setup time
TCSS
50
ns Relative to CLK
Chip select hold time
TCSH
0
— ns Relative to CLK
Chip select low time
TCSL
250
ns
Data input setup time
TDIS
100
ns Relative to CLK
Data input hold time
TDIH
100
ns Relative to CLK
Data output delay time
TPD — 400 ns Cl = 100 pF
Data output disable time
TCZ — 100 ns Cl = 100 pF (Note 2)
Status valid time
TSV — 500 ns Cl = 100 pF
TWC
6 ms ERASE/WRITE mode
Program cycle time
TEC
6 ms ERAL mode
TWL
15 ms WRAL mode
Endurance
— 1M — cycles 25°C, VCC = 5.0V, Block Mode (Note 3)
Note 1:
2:
3:
This parameter is tested at Tamb = 25°C and FCLK = 1 MHz.
This parameter is periodically sampled and not 100% tested.
This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total
Endurance Model which may be obtained on Microchip’s BBS or website.
DS21208A-page 2
Preliminary
© 1997 Microchip Technology Inc.

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2.0 PIN DESCRIPTION
2.1 Chip Select (CS)
A high level selects the device; a low level deselects the
device and forces it into standby mode. However, a pro-
gramming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93LC56A/B.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
93LC56A/B
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a START condition the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (Table 2-1
and Table 2-2). CLK and DI then become don't care
inputs waiting for a new START condition to be
detected.
2.3 Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4 Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation has
been initiated.
The status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
TABLE 2-1 INSTRUCTION SET FOR 93LC56A
Instruction SB Opcode
Address
Data In
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
1
1
1
1
1
1
1
11
X A7 A6 A5 A4 A3 A2 A1 A0
00 1 0 X X X X X X X —
00 0 0 X X X X X X X —
00 1 1 X X X X X X X —
10
X A7 A6 A5 A4 A3 A2 A1 A0
01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0
00 0 1 X X X X X X X D7 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D7 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
12
12
12
12
20
20
20
TABLE 2-2 INSTRUCTION SET FOR 93LC56B
Instruction SB Opcode
Address
Data In
ERASE 1
11
X A6 A5 A4 A3 A2 A1 A0
ERAL
1
00
1 0XXXXXX
EWDS 1 00 0 0 X X X X X X —
EWEN 1 00 1 1 X X X X X X —
READ 1
10
X A6 A5 A4 A3 A2 A1 A0
WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0
WRAL 1 00 0 1 X X X X X X D15 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D15 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
11
11
11
11
27
27
27
© 1997 Microchip Technology Inc.
Preliminary
DS21208A-page 3

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93LC56A/B
3.0 FUNCTIONAL DESCRIPTION
Instructions, addresses and write data are clocked into
the DI pin on the rising edge of the clock (CLK). The DO
pin is normally held in a HIGH-Z state except when
reading data from the device, or when checking the
READY/BUSY status during a programming operation.
The READY/BUSY status can be verified during an
ERASE/WRITE operation by polling the DO pin; DO
low indicates that programming is still in progress, while
DO high indicates the device is ready. The DO will enter
the HIGH-Z state on the falling edge of the CS.
3.1 START Condition
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE,
and WRAL). As soon as CS is high, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new START condition is
detected.
3.2 DATA IN (DI) AND DATA OUT (DO)
It is possible to connect the Data In (DI) and Data Out
(DO) pins together. However, with this configuration, if
A0 is a logic-high level, it is possible for a “bus conflict”
to occur during the “dummy zero” that precedes the
READ operation. Under such a condition, the voltage
level seen at DO is undefined and will depend upon the
relative impedances of DO and the signal source driv-
ing A0. The higher the current sourcing capability of A0,
the higher the voltage at the DO pin.
3.3 Data Protection
During power-up, all programming modes of operation
are inhibited until Vcc has reached a level greater than
2.2V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fallen below 2.2V at nominal conditions.
The EWDS and EWEN commands give additional pro-
tection against accidentally programming during
normal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
FIGURE 3-1: SYNCHRONOUS DATA TIMING
CS VIH
VIL
VIH
CLK
VIL
VIH
DI
VIL
TDIS
TCSS
DO VOH
(READ) VOL
DO VOH
(PROGRAM)
VOL
TSV
TCKH
TDIH
TPD
Note: AC Test Conditions: VIL = 0.4V, VIH - 2.4V.
TCKL
STATUS VALID
TPD
TCSH
TCZ
TCZ
DS21208A-page 4
Preliminary
© 1997 Microchip Technology Inc.

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3.4 ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
FIGURE 3-2: ERASE TIMING
CS
CLK
93LC56A/B
3.5 Erase All (ERAL)
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identical
to the ERASE cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences at
the falling edge of the CS. Clocking of the CLK pin is not
necessary after the device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire ERAL cycle is com-
plete.
TCSL
CHECK STATUS
DI
1
1
1
AN AN-1 AN-2 •••
A0
HIGH-Z
DO
FIGURE 3-3: ERAL TIMING
CS
TCSL
TSV
BUSY
TWC
TCZ
READY
HIGH-Z
CHECK STATUS
CLK
DI
1
00
10
X •••
X
HIGH-Z
DO
Guaranteed at Vcc = 4.5V to +6.0V.
TSV
BUSY
TEC
TCZ
READY
HIGH-Z
© 1997 Microchip Technology Inc.
Preliminary
DS21208A-page 5