93LC66.pdf 데이터시트 (총 20 페이지) - 파일 다운로드 93LC66 데이타시트 다운로드

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Not recommended for new designs –
Please use 93LC46C, 93LC56C or 93LC66C.
93LC46/56/66
1K/2K/4K 2.5V Microwire Serial EEPROM
Features:
• Single supply with programming operation down
to 2.5V
• Low-power CMOS technology
• 100 A typical active read current at 2.5V
• 3 A typical standby current at 2.5V
• ORG pin selectable memory configuration
• 128 x 8- or 64 x 16-bit organization (93LC46)
• 256 x 8- or 128 x 16-bit organization (93LC56)
• 512 x 8 or 256 x 16 bit organization (93LC66)
• Self-timed erase and write cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during erase/write cycles
• Sequential read function
• 1,000,000 E/W cycles ensured
• Data retention > 200 years
• 8-pin PDIP/SOIC
(SOIC in JEDEC standards)
• Temperature ranges supported:
- Industrial (I):
-40°C to +85°C
Description:
The Microchip Technology Inc. 93LC46/56/66 are 1K,
2K and 4K low voltage serial Electrically Erasable
PROMs (EEPROM). The device memory is configured
as x8 or x16 bits depending on the external logic of
levels of the ORG pin. Advanced CMOS technology
makes these devices ideal for low power nonvolatile
memory applications. The 93LC Series is available in
standard 8-pin PDIP and surface mount SOIC
packages. The rotated pin-out 93LC46X/56X/66X are
offered in the “SN” package only.
Package Types
PDIP/SOIC
CS 1
CLK 2
DI 3
DO 4
ROTATED SOIC
NU
VCC
CS
CLK
1
2
3
4
8 VCC
7 NU
6 ORG
5 VSS
8 ORG
7 VSS
6 DO
5 DI
Block Diagram
VCC VSS
Memory
Array
DI
ORG
CS
CLK
Data Register
Mode
Decode
Logic
Clock
Register
Address
Decoder
Address
Counter
Output
Buffer
DO
2002-2012 Microchip Technology Inc.
DS21712C-page 1

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93LC46/56/66
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins  4 kV
† NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
DC CHARACTERISTICS
DC CHARACTERISTICS
VCC = +2.5V to +5.5V
Industrial (I): TA = -40°C to +85°C
Param.
No.
Sym
Characteristic
Min Typ Max
D1 VIH1 High-level input voltage 2.0
— VCC +1
VIH2
0.7 VCC — VCC +1
D2 VIL1
Low-level input voltage
-0.3
0.8
VIL2
-0.3 — 0.2 VCC
D3 VOL1 Low-level output voltage —
— 0.4
VOL2
— — 0.3
D4 VOH1 High-level output voltage 2.4 — —
VOH2
VCC -0.2 —
D5 ILI
Input leakage current
— — ±10
D6 ILO
Output leakage current
— ±10
D7 CIN,
Pin capacitance
COUT (all inputs/outputs)
—— 7
D8 ICC write Operating current
——
3
D9 ICC read
D10 ICCS
Standby current
—— 1
— — 500
— 100 —
— — 100
— — 30
—3—
Note 1: This parameter is tested at TA = 25°C and FCLK = 1 MHz.
2: This parameter is periodically sampled and not 100% tested.
Units
Conditions
V VCC 2.7V
V VCC 2.7V
V VCC 2.7V
V VCC 2.7V
V IOL = 2.1 mA, VCC = 4.5V
V IOL = 100 A, VCC = 2.5V
V IOL = 400 A, VCC = 4.5V
V IOL = 100 A, VCC = 2.5V
A VIN = 0.1V to VCC
A VOUT = 0.1V to VCC
pF VIN/VOUT = 0V (Note 1 & 2)
TA = 25°C, FCLK = 1 MHz
mA FCLK = 2 MHz, VCC = 5.5V
(Note 2)
mA FCLK = 2 MHz, VCC = 5.5V
A FCLK = 1 MHz, VCC = 3.0V
A FCLK = 1 MHz, VCC = 2.5V
A CLK = CS = 0V; VCC = 5.5V
A CLK = CS = 0V; VCC = 3.0V
A CLK = CS = 0V; VCC = 2.5V
ORG, DI = VSS or VCC
DS21712C-page 2
2002-2012 Microchip Technology Inc.

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93LC46/56/66
AC CHARACTERISTICS
AC CHARACTERISTICS
VCC = +2.5V to +5.5V
Industrial (I): TA = -40°C to +85°C
Param.
No.
Sym
Characteristic
Min Typ Max Units
Conditions
1
FCLK
Clock frequency
— — 2 MHz VCC 4.5V
— — 1 MHz VCC 4.5V
2
TCKH
Clock high time
250 — — ns
3
TCKL
Clock low time
250 — — ns
4
TCSS
Chip select setup time
50
— — ns Relative to CLK
5
TCSH
Chip select hold time
0 — — ns Relative to CLK
6
TCSL
Chip select low time
250 — — ns
7
TDIS
Data input setup time
100 — — ns Relative to CLK
8
TDIH
Data input hold time
100 — — ns Relative to CLK
9 TPD Data output delay time — — 400 ns CL = 100 pF
10 TCZ
Data output disable time
— 100 ns CL = 100 pf (Note 2)
11 TSV
Status valid time
12 TWC Program cycle time
13 TEC
14 TWL
15 —
Endurance
— — 500 ns CL = 100 pF
— 4 10 ms Erase/Write mode
— 8 15 ms ERAL mode (VCC=5V ±10%)
— 16 30 ms WRAL mode (VCC=5V ±10%)
1M — 1M cycles 25°C, VCC = 5.0V, Block
mode (Note 3)
Note 1:
2:
3:
This parameter is tested at TA = 25°C and FCLK = 1 MHz.
This parameter is periodically sampled and not 100% tested.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total EnduranceModel which can be obtained from Microchip’s web site
at: www.microchip.com.
FIGURE 1-1:
SYNCHRONOUS DATA TIMING
CS VIH
VIL
VIH
CLK
VIL
VIH
DI
VIL
DO VOH
(Read) VOL
DO VOH
(Write) VOL
42
78
9
11
3
9
Status Valid
5
10
10
2002-2012 Microchip Technology Inc.
DS21712C-page 3

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93LC46/56/66
TABLE 1-1: INSTRUCTION SET FOR 93LC46: ORG = 1 (X 16 ORGANIZATION)
Instruction SB
Opcode
Address
Data In
Data Out
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
1 10 A5 A4 A3 A2 A1 A0
1 00 1 1 XXXX
1 11 A5 A4 A3 A2 A1 A0
1 00 1 0 XXXX
1 01 A5 A4 A3 A2 A1 A0
1 00 0 1 XXXX
1 00 0 0 XXXX
D15 - D0
D15 - D0
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
TABLE 1-2: INSTRUCTION SET FOR 93LC46: ORG = 0 (X 8 ORGANIZATION)
Instruction SB
Opcode
Address
Data In
Data Out
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
1 10 A6 A5 A4 A3 A2 A1 A0
1 00 1 1 X X X X X
1 11 A6 A5 A4 A3 A2 A1 A0
1 00 1 0 X X X X X
1 01 A6 A5 A4 A3 A2 A1 A0
1 00 0 1 X X X X X
1 00 0 0 X X X X X
D7 - D0
D7 - D0
D7 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
TABLE 1-3: INSTRUCTION SET FOR 93LC56: ORG = 1 (X 16 ORGANIZATION)
Instruction SB
Opcode
Address
Data In
Data Out
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
1 10 X A6 A5 A4 A3 A2 A1 A0
1 00 1 1 X X X X X X
1 11 X A6 A5 A4 A3 A2 A1 A0
1 00 1 0 X X X X X X
1 01 X A6 A5 A4 A3 A2 A1 A0
1 00 0 1 X X X X X X
1 00 0 0 X X X X X X
D15 - D0
D15 - D0
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
TABLE 1-4: INSTRUCTION SET FOR 93LC56: ORG = 0 (X 8 ORGANIZATION)
Instruction SB
Opcode
Address
Data In
Data Out
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
1 10 X A7 A6 A5 A4 A3 A2 A1 A0
— D7 - D0
1 00 1 1 X X X X X X X
— High-Z
1 11 X A7 A6 A5 A4 A3 A2 A1 A0
— (RDY/BSY)
1 00 1 0 X X X X X X X
— (RDY/BSY)
1
01 X A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0 (RDY/BSY)
1 00 0 1 X X X X X X X
D7 - D0 (RDY/BSY)
1 00 0 0 X X X X X X X
— High-Z
Req. CLK
Cycles
25
9
9
9
25
25
9
Req. CLK
Cycles
18
10
10
10
18
18
10
Req. CLK
Cycles
27
11
11
11
27
27
11
Req. CLK
Cycles
20
12
12
12
20
20
12
DS21712C-page 4
2002-2012 Microchip Technology Inc.

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93LC46/56/66
TABLE 1-5: INSTRUCTION SET FOR 93LC66: ORG = 1 (X 16 ORGANIZATION)
Instruction SB
Opcode
Address
Data In
Data Out
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
1 10 A7 A6 A5 A4 A3 A2 A1 A0
1 00 1 1 X X X X X X
1 11 A7 A6 A5 A4 A3 A2 A1 A0
1 00 1 0 X X X X X X
1 01 A7 A6 A5 A4 A3 A2 A1 A0
1 00 0 1 X X X X X X
1 00 0 0 X X X X X X
D15 - D0
D15 - D0
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK
Cycles
27
11
11
11
27
27
11
TABLE 1-6: INSTRUCTION SET FOR 93LC66: ORG = 0 (X 8 ORGANIZATION)
Instruction SB
Opcode
Address
Data In
Data Out
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
1 10 A8 A7 A6 A5 A4 A3 A2 A1 A0
— D7 - D0
1 00 1 1 X X X X X X X
— High-Z
1 11 A8 A7 A6 A5 A4 A3 A2 A1 A0
— (RDY/BSY)
1 00 1 0 X X X X X X X
— (RDY/BSY)
1
01 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0 (RDY/BSY)
1 00 0 1 X X X X X X X
D7 - D0 (RDY/BSY)
1 00 0 0 X X X X X X X
— High-Z
Req. CLK
Cycles
20
12
12
12
20
20
12
2002-2012 Microchip Technology Inc.
DS21712C-page 5