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PS11PS01115015
FLAFTL-BATA-SBEASTEYPTEYPE
INSIUNLSAUTLEADTETDYPTEYPE
PS11015
INTEGRATED FUNCTIONS AND FEATURES
• Converter bridge for 3 phase AC-to-DC power conversion.
• Circuit for dynamic braking of motor regenerative energy.
• 3-phase IGBT inverter bridge configured by the latest 3rd.
generation IGBT and diode technology.
• Inverter output current capability IO (Note 1):
Type Name
100% load
150% over load
PS11015
7.0A (rms)
10.5A (rms), 1min
(Note 1) : The inverter output current is assumed to be sinu-
soidal and the peak current value of each of the
above loading cases is defined as : IOP = IO × √2
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• For inverter side upper-leg IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short circuit protection (SC).
Bootstrap circuit supply scheme (single drive power supply) and Under voltage protection (UV).
• For inverter side lower-leg IGBTs : Drive circuit, Short circuit protection (SC).
Control supply circuit under- & over- voltage protection (OV/UV).
System over temperature protection (OT). Fault output signaling circuit (FO) and Current limit warn-
ing signal output (CL).
• For Brake circuit IGBT : Drive circuit
• Warning and Fault signaling :
FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through.
FO2 : N-side control supply abnormality locking (OV/UV).
FO3 : System over-temperature protection (OT).
CL : Warning for inverter current overload condition
• For system feedback control : Analogue signal feedback reproducing actual inverter output phase currents (3φ).
• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.
APPLICATION
Acoustic noise-less 1.5kW/AC200V class 3 phase inverter and other motor control applica-
tions
PACKAGE OUTLINES
4-R2
0.5
1 2 3 4 5 6 7 8 91011121314151617181920212223
24
2424
2 ± 0.3
2-φ4
2-R4
5.08 ± 0.3 ! 9 = 45.72 ± 0.8
31 32 33 34 35 36 37 38 39 40
1.2
(Fig. 1)
LABEL
54 ± 0.5
62 ± 1
V6
Terminals Assignment:
1 CBU+
2 CBU–
3 CBV+
4 CBV–
5 CBW+
6 CBW–
7 GND
8 NC
9 VDH
10 CL
11 FO1
12 FO2
13 FO3
14 CU
15 CV
16 CW
17 UP
18 VP
19 WP
20 UN
21 VN
22 WN
23 Br
31 R
32 S
33 T
34 P1
35 P2
36 N
37 B
38 U
39 V
40 W
V Control Pin top
portion details
0.3
0.5 ± 0.03
V Main terminal top
portion details
0.8
±
0.5
0
0.35MAX
12
±
0.5
0
0.6
Jan. 2000

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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11015
FLAT-BASE TYPE
INSULATED TYPE
INTERNAL FUNCTIONS BLOCK DIAGRAM
C3 ; 3.3µF or more, tight tolerance, temp-compensated electrolytic type (Note : the value may change
depending on the type PWM control scheme used in the applied system)
C4 ; 2µF R-category ceramic condenser for noise filtering.
Application Specific Intelligent
Power Module
Brake resistor
P2
connection,
B
Inrush prevention
circuit, etc.
P1
Protection
Circuit
Level shifter
Drive Circuit
AC200V line input
R
S
T
U
MV
W
ZC
N
T.S. AC 200V line
output
Z : Surge absorber.
C : AC filter (Ceramic condenser 2.2~6.5nF)
[Note : Additionally an appropriate Line-to line
surge absorber circuit maybe necessary
depending on the application environment].
Current sensing
circuit
Trig signal conditioning
Drive Curcuit
FO Logic Protection
circuit
Control supply
fault sense
CU CV CW
UPVPWPUN VNWN Br CL FO1 FO2 FO3
C2 ;
C2 3.3µF or more
Analogue signal output corresponding to Each phase input (PWM) Fault output
each phase current (5V line) Note 1)
(5V line) Note 2) (5V line) Note 3)
GND VDH
(15V line)
Note 1) To prevent chances of signal oscillation, an RC coupling at each output is recommended. (see also Fig.10)
Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU, without any opto or transformer isolation ispossible. (see also Fig.10)
Note 3) All these outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kresistance. (see also Fig.10)
Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra
precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC powerinput pins.
(Fig. 2)
MAXIMUM RATINGS (Tj = 25°C)
INVERTER PART (Including Brake Part)
Symbol
VCC
VCC(surge)
VP or VN
VP(S) or VN(S)
±IC(±ICP)
IC(ICP)
IF(IFP)
Item
Supply voltage
Supply voltage (surge)
Each output IGBT collector-emitter static voltage
Each output IGBT collector-emitter
switching surge voltage
Each output IGBT collector current
Brake IGBT collector current
Brake diode anode current
Condition
Applied between P2-N
Applied between P2-N, Surge-value
Applied between P-U, V, W, Br or U, V, W,
Br-N
Applied between P-U, V, W, Br or U, V, W,
Br-N
TC = 25°C
Note: “( )” means IC peak value
CONVERTER PART
Symbol
VRRM
Ea
IO
IFSM
I2t
Item
Repetitive peak reverse voltage
Recommended AC input voltage
DC output current
Surge (non-repetitive) forward current
I2t for fusing
Condition
3φ rectifying circuit
1 cycle at 60Hz, peak value non-repetitive
Value for one cycle of surge current
CONTROL PART
Symbol
VDH, VDB Supply voltage
Item
VCIN
VFO
IFO
VCL
ICL
ICO
Input signal voltage
Fault output supply voltage
Fault output current
Current-limit warning (CL) output voltage
CL output current
Analogue current signal output current
Condition
Applied between VDH-GND, CBU+-CBU–,
CBV+-CBV–, CBW+-CBW–
Applied between UP · VP · WP · UN · VN ·
WN · Br-GND
Applied between FO1 · FO2 · FO3-GND
Sink current of FO1 · FO2 · FO3
Applied between CL-GND
Sink current of CL
Sink current of CU · CV · CW
Ratings
450
500
600
600
±20 (±40)
8 (16)
8 (16)
Ratings
800
220
25
196
160
Ratings
20
–0.5 ~ 7.5
–0.5 ~ 7
15
–0.5 ~ 7
15
±1
Unit
V
V
V
V
A
A
A
Unit
V
V
A
A
A2s
Unit
V
V
V
mA
V
mA
mA
Jan. 2000

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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11015
FLAT-BASE TYPE
INSULATED TYPE
TOTAL SYSTEM
Symbol
Item
Condition
Ratings
Unit
Tj Junction temperature
(Note 2)
–20 ~ +125
°C
Tstg Storage temperature
–40 ~ +125
°C
TC Module case operating temperature
(Fig. 3)
–20 ~ +100
°C
Viso Isolation voltage
60 Hz sinusoidal AC applied between all terminals and
the base plate for 1 minute.
2500
Vrms
— Mounting torque
Mounting screw: M3.5
0.78 ~ 1.27
kg·cm
Note 2) The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. How-
ever, these power elements can endure junction temperature as high as 150°C instantaneously . To make use of this additional tem-
perature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is requested
to be provided before use.
CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface)
TC
(Fig. 3)
THERMAL RESISTANCE
Symbol
Item
Rth(j-c)Q
Rth(j-c)F
Rth(j-c)QB
Rth(j-c)FB
Rth(j-c)FR
Rth(c-f)
Junction to case Thermal
Resistance
Contact Thermal Resistance
Condition
Inverter IGBT (1/6)
Inverter FWDi (1/6)
Brake IGBT
Brake FWDi
Converter Di (1/6)
Case to fin, thermal grease applied (1 Module)
Ratings
Min. Typ. Max.
Unit
— — 2.3 °C/W
— — 3.1 °C/W
— — 4.0 °C/W
— — 6.0 °C/W
— — 4.3 °C/W
— — 0.044 °C/W
ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted)
Symbol
VCE(sat)
VEC
Item Condition
Collector-emitter saturation voltage VDH = VDB = 15V, Input = ON, Tj = 25°C, IC = 20A
FWDi forward voltage
Tj = 25°C, IC = –20A, Input = OFF
Ratings
Min. Typ. Max.
— — 2.9
— — 2.9
Unit
V
V
VCE(sat)Br
VFBr
IRRM
VFR
ton
tc(on)
toff
tc(off)
trr
Brake IGBT
Collector-emitter saturation voltage
VDH = 15V, Input = ON, Tj = 25°C, IC = 8A
Brake diode forward voltage Tj = 25°C, IF = 8A, Input = OFF
Converter diode reverse current VR = VRRM, Tj = 125°C
Converter diode voltage
Tj = 25°C, IF = 10A
1/2 Bridge inductive load, Input = ON
Switching times
VCC = 300V, Ic = 20A, Tj = 125°C
VDH = 15V, VDB = 15V
FWD reverse recovery time
Note : ton, toff include delay time of the internal control
circuit
Short circuit endurance
VCC 400V, Input = ON (one-shot)
(Output, Arm, and Load,
Tj = 125°C start
Short Circuit Modes)
13.5V VDH = VDB 16.5V
VCC 400V, Tj 125°C,
Switching SOA
Ic < IOL(CL) operation level, Input = ON
13.5V VDH = VDB 16.5V
— — 3.5 V
— — 2.9 V
——
8 mA
— — 1.5 V
0.3 0.6 1.5 µs
— 0.2 0.6 µs
— 1.1 1.8 µs
— 0.4 1.0 µs
— 0.1 — µs
• No destruction
• FO output by protection operation
• No destruction
• No protecting operation
• No FO output
Jan. 2000

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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11015
FLAT-BASE TYPE
INSULATED TYPE
ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted)
Symbol
Item
Condition
IDH Circuit current
Vth(on)
Input on threshold voltage
Vth(off)
Input off threshold voltage
Ri
fPWM
Input pull-up resistor
PWM input frequency
txx Allowable input on-pulse width
tdead
Allowable input signal dead time for
blocking arm shoot-through
tint Input inter-lock sensing
VCO
VC+(200%)
Analogue signal linearity with
output current
VC–(200%)
|VCO| Offset change area vs temperature
VC+ Analogue signal output voltage limit
VC–
VC(200%) Analogue signal over all linear variation
rCH Analogue signal data hold accuracy
td(read)
±IOL
ICL(H)
ICL(L)
SC
OT
OTr
UVDH
UVDHr
OVDH
OVDHr
UVDB
UVDBr
tdV
IFO(H)
IFO(L)
Analogue signal reading time
Current limit warning (CL) operation level
Signal output current of
CL operation
Idle
Active
Short circuit over current trip level
Trip level
Over temperature protection
Reset level
Trip level
Reset level
Supply circuit under &
over voltage protection
Trip level
Reset level
Trip level
Reset level
Filter time
Fault output current
Idle
Active
VDH = 15V, VCIN = 5V
Integrated between input terminal-VDH
TC 100°C, Tj 125°C
VDH = 15V, TC = –20°C ~ +100°C (Note 3)
Relates to corresponding input
(Except brake part) TC = –20°C ~ +100°C
Relates to corresponding input (Except brake part)
Ic = 0A
Ic = IOP(200%)
Ic = –IOP(200%)
VDH = 15V
TC = –20°C ~ +100°C
(Fig. 4)
VDH = 15V, TC = –20°C ~ +100°C
Ic > IOP(200%), VDH = 15V
(Fig. 4)
|VCO-VC±(200%)|
Correspond to max. 500µs data hold period
only, Ic = IOP(200%)
(Fig. 5)
After input signal trigger point
(Fig. 8)
VDH =15V, TC = –20°C ~ +100°C (Note 4)
Open collector output
Tj = 25°C
(Fig. 7) (Note 5)
VDH =15V
TC = –20°C ~ +100°C
Tj 125°C
Open collector output
Min.
0.8
2.5
2
1
2.2
1.87
0.77
2.97
4.0
–5
20.35
30.0
100
11.05
11.55
18.00
16.50
10.0
10.5
Ratings
Typ.
1.4
3.0
150
65
2.27
1.17
3.37
15
1.1
3
24.70
1
53.0
110
90
12.00
12.50
19.20
17.50
11.0
11.5
10
1
Max.
150
2.0
4.0
20
500
100
2.57
1.47
3.67
0.7
5
29.00
1
76.0
120
12.75
13.25
20.15
18.65
12.0
12.5
1
Unit
mA
V
V
k
kHz
µs
µs
ns
V
V
V
mV
V
V
V
%
µs
A
µA
mA
A
°C
°C
V
V
V
V
V
V
µs
µA
mA
(Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only.
(b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit.
(Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The
circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme.
(Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen-
tarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is
not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to
excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri-
ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut
down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back
from its FO1 pin of the ASIPM indicating a short circuit situation.
RECOMMENDED CONDITIONS
Symbol
Item
VCC Supply voltage
VDH, VDB Control supply voltage
VDH, VDB
VCIN(on)
VCIN(off)
fPWM
tdead
Supply voltage ripple
Input on voltage
Input off voltage
PWM Input frequency
Arm shoot-through blocking time
Condition
Applied across P2-N terminals
Applied between VDH-GND, CBU+-CBU–, CBV+-CBV–,
CBW+-CBW–
Using application circuit
Using application circuit
Ratings
400 (max.)
15±1.5
±1 (max.)
0 ~ 0.3
4.8 ~ 5.0
2 ~ 20
2.2 (min.)
Unit
V
V
V/µs
V
V
kHz
µs
Jan. 2000

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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11015
FLAT-BASE TYPE
INSULATED TYPE
Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING
LINEARITY
5
VC
4 min max
VC(200%)
VDH=15V
TC=20~100˚C
3
VC0
2
VC+(200%)
1
Analogue output signal
data hold range
VC+
0
–400 –300 –200 –100 0 100 200 300 400
Real load current peak value.(%)(Ic=Io! 2)
(Fig. 4)
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
VC
500µs
0V VCH(5µs)
VCH(505µs)
rCH=
VCH(505µs)-VCH(5µs)
VCH(5 µs)
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5 µs delayed point.
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Input signal VCIN(p) of each phase upper arm 0V
Input signal VCIN(n) of each phase lower arm
Gate signal Vo(p) of each phase upper arm
(ASIPM internal)
0V
0V
Gate signal Vo(n) of each phase upper arm
(ASIPM internal)
0V
Error output FO1 0V
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “FO” signal is outputted. After an “input
interlock” operation the circuit is latched. The “FO” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Input signal VCIN of each phase
upper arm
0V
Short circuit sensing signal VS
Gate signal Vo of each phase
upper arm(ASIPM internal)
0V
0V
Error output FO1 0V
SC delay time
Note : Short circuit protection operation. The protection operates with “FO” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
Jan. 2000