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NTE6850
Integrated Circuit
NMOS, Asynchronous Communications
Interface Adapter
Description:
The NTE6850 Asynchronous Communications Interface Adapter provides the data formatting and
control to interface serial asynchronous data communications information to bus organized systems
such as the NTE6800 Microprocessing Unit.
The bus interface of the NTE6850 includes select, enable, read/write, interrupt and bus interface logic
to allow data transfer over an 8–bit bidirectional data bus. The parallel data of the bus system is serial-
ly transmitted and received by the asynchronous data interface, with proper formatting and error
checking. The functional configuration of the ACIA is programmed via the data bus during system
initialization. A programmable control register provides variable word lengths, clock division ratios,
transmit control, receive control, and interrupt control. For peripheral or modem operation, three con-
trol lines are provided. These lines allow the ACIA to interface directly with the NTE6860 0–600 bps
digital modem.
Features:
D 8–Bit and 9–Bit Transmission
D Optional Even and Odd Parity
D Parity, Overrun and Framing Error Checking
D Programmable Control Register
D Optional ÷1, ÷16, and ÷64 Clock Modes
D Up to 1.0 Mbps Transmission
D False Start Bit Deletion
D Peripheral/Modem Control Functions
D Double Buffered
D One–Stop or Two–Stop Bit Operation
Absolute Maximum Ratings:
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0V
Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0V
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to 70°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C
Thermal Resistance, Junction–to–Ambient, RthJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum rated voltages to this high impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.
either VSS or VCC).

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Electrical Characteristics: (VCC = 5V ± 5%, VSS = 0, TA = 0° to +70°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Input High Voltage
VIH
VSS+2.0 VCC V
Input Low Voltage
Input Leakage Current
R/W, CS0, CS1, CS2,
Enable, RS, RX D, RX C,
CTS, DCD
VIL
Iin Vin = 0 to 5.25V
VSS0.3 VSS+0.8 V
1.0 2.5 µA
HiZ (OffState) Input Current
D0 D7
ITSI Vin = 0.4 to 2.4V
2.0 10.0 µA
Output High Voltage
D0 D7
VOH ILoad = 205µA, Enable Pulse Width < 25µs VSS+2.4 – – V
Output High Voltage
TX Data, RTS
Output Low Voltage
Output Leakage Current
(OffState) IRQ
ILoad = 100µA, Enable Pulse Width < 25µs VSS+2. – – V
VOL ILoad = 1.6A, Enable Pulse Width < 25µs
ILOH VOH = 2.4V
– – VSS+0.4 V
1.0 10 µA
Internal Power Dissipation
Internal Input Capacitance
D0 D7
PINT TA = 0°C, Note 2
Cin Vin = 0, TA = +25°C, f = 1MHz
300 525 mW
10.0 12.5 pF
Internal Input Capacitance
E, TX CLK, RX CLK, R/W,
RS, RX Data, CS0, CS1,
CS2, CTS, DCD
7.0 7.5 pF
Output Capacitance
RTS, TX Data
Output Capacitance
IRQ
Cout Vin = 0, TA = +25°C, f = 1MHz
– – 10 pF
– – 5 pF
Note 2. For temperatures less than TA = 0°C, PINT maximum will increase.
Serial Data Timing Characteristics:
Parameter
Symbol
Test Conditions
Data Clock Pulse Width, Low
PWCL B16, B64 Modes
B1 Mode
Data Clock Pulse Width, High
PWCH B16, B64 Modes
B1 Mode
Data Clock Frequency
fC B16, B64 Modes
B1 Mode
Data ClocktoData Delay for Transmitter
Receive Data Setup Time
Receive Data Hold Time
Interrupt Request Release Time
RequesttoSend Delay Time
Input Rise and Fall Times
tTDD
tRDS
tRDH
tR
tRTS
tr, tf
B1 Mode
B1 Mode
or 10% of the pulse width if smaller
Min Typ Max Unit
600 450 ns
900 650 ns
600 450 ns
900 650 ns
– – 0.8 MHz
– – 500 kHz
– – 600 ns
250 – – ns
250 – – ns
– – 1.2 µs
– – 560 ns
– – 1.0 µs

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Bus Timing Characteristics: (VL 4V, VH 2.4V, measurement points 0.8V and 2V unless
otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Cycle Time
Pulse Width, E Low
Pulse Width, E High
Clock Rise and Fall Time
Address Hold Time
Address Setup Time Before E
Chip Select Setup Time Before E
Chip Select Hold Time
Read Data Hold Time
Write Data Hold Time
Output data Delay Time
Input Data Setup Time
tcyc
PWEL
PWEH
tr, tf
tAH
tAS
tCS
tCH
tDHR
tDHW
tDHW
tDSW
Note 3
1.0 10.0 µs
430 9500 ns
450 9500 ns
– – 25 ns
10 – – ns
80 – – ns
80 – – ns
10 – – ns
20 50 ns
10 – – ns
– – 290 ns
165 – – ns
Note 3. The data bus output buffers are no longer sourcing or sinking current by tDHRmax (High
Impedance).
Pin Connection Diagram
VSS 1
Rx Data 2
Cx Clk 3
Tx Clk 4
RTS 5
Tx Data 6
IRQ 7
CS0 8
CS2 9
CS1 10
RS 11
VDD 12
24 CTS
23 DCD
22 D0
21 D1
20 D2
19 D3
18 D4
17 D5
16 D6
15 D7
14 E
13 R/W
24 13
1 12
1.300 (33.02)
Max
.100 (2.54)
1.100 (27.94)
.225
(5.73)
Max
.520
(13.2)
.126
(3.22)
Min
.600
(15.24)