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OCX160 Crosspoint Switch
Preliminary Data Sheet
Features
667 Mb/s port data bandwidth, >50Gb/s aggregate bandwidth Full Broadcast and multicast capability
Low power CMOS, 2.5V and 3.3V power supply
SRAM-based, in-system programmable
160 configurable I/O ports
80 dedicated differential input ports
80 dedicated differential output ports
Supports LVDS and LVPECL I/O
LVTTL control interface
Output Enable control for all outputs
Non-blocking switch matrix
Patented ActiveArraymatrix for superior performance
Double-buffered configuration RAM cells for simultaneous
global updates
One-to-One and One-to-Many connections
Special broadcast mode routes one input to
all outputs at maximum data rate
Registered and flow-through data modes
333 MHz synchronous mode
667 Mb/s asynchronous mode
Low jitter and signal skew
Low duty cycle distortion
RapidConfigureparallel interface for
configuration and readback
JTAG serial interface for configuration and
Boundary Scan testing
ImpliedDisconnectfunction for single cycle disconnect/ 420 BGA package with 1.27mm ball spacing
connect
Description
The OCX™ family of SRAM-based devices are non-blocking n X n digital crosspoint switches capable of data
rates of 667 Megabits per second per port. The I/O ports are fixed as either input or output ports. The input ports
support flow-through mode only. The output ports are individually programmable to operate in either flow-
through (asynchronous) or registered (synchronous) mode. Each output register may be clocked by a global
clock or a next neighbor clock source.
The patented ActiveArray provides greater density, superior performance, and greater flexibility compared to a
traditional n:1 multiplexer architecture. The OCX devices support various operating modes covering one input to
one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to
all outputs while maintaining maximum data rates. In all modes data integrity and connections are maintained on
all unchanged data paths.
The RapidConfigure parallel interface allows fast configuration of both the Output Buffers and the switch
matrix. Readback is supported for device test and verification purposes. The OCX160 also supports the industry
standard JTAG (IEEE 1149.1) interface for boundary scan testing. The JTAG interface can also be used to
download configuration data to the device and readback data. A functional block diagram of the OCX160 is
shown in Figure 1.
Applications
SONET/SDH and DWDM
Digital Cross-Connects
System Backplanes and Interconnects
High Speed Test Equipment
ATM Switch Cores
Video Switching
160
IN[79:0]
Input
Buffers
80 x 80
Crosspoint
Switch Matrix
Output
Buffers
160
OUT[79:0]
2 CLK
OE#
RapidConfigure
Signals
RCA[6:0] 7
RCB[6:0] 7
RCI[3:0] 4
RCO[4:0] 5
RC_CLK#
RC_EN#
UPDATE#
Configuration and
Programming Logic
TCK
TMS
TDI
TRST#
TDO
JTAG
Signals
HW_RST#
Figure 1 OCX160 Functional Block Diagram
I-Cube, Inc.
[Rev. 1.6] 2/20/01
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OCX160 Crosspoint SwitchPreliminary Data Sheet
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I-Cube, Inc.

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OCX160 Crosspoint SwitchPreliminary Data Sheet
Contents
1. Introduction ........................................................................................................................... 7
1.1 Input and Output Buffers...................................................................................................... 8
1.1.1 Input and Output Port Function Mode ........................................................................... 8
1.1.2 Broadcast Mode ............................................................................................................. 9
1.2 Output Buffer Configuration ................................................................................................ 9
1.2.1 Output Control Signals................................................................................................... 9
1.2.2 Neighboring Output Port as a Clock Source .................................................................. 9
1.3 RapidConfigure Interface ....................................................................................................11
1.3.1 RapidConfigure Programming Instructions.................................................................. 11
1.3.2 ImpliedDisconnect ....................................................................................................... 13
1.4 JTAG Configuration Controller.......................................................................................... 14
1.4.1 JTAG Interface............................................................................................................. 14
1.4.2 Output Port Configuration ........................................................................................... 14
1.4.3 Switch Matrix Configuration ....................................................................................... 14
1.4.4 Mode Control Register Configuration.......................................................................... 14
1.4.5 JTAG Architecture and Shift Registers ........................................................................ 15
1.4.6 JTAG State Machine .................................................................................................... 16
1.4.7 JTAG Input Format ...................................................................................................... 16
1.4.8 JTAG Instructions ........................................................................................................ 17
1.5 Device Reset Options ......................................................................................................... 20
2. Pin Description .....................................................................................................................21
3. Differential I/O Standards ...................................................................................................22
3.1 LVDS ................................................................................................................................. 22
3.2 LVPECL ............................................................................................................................. 23
3.3 Termination Resistor Packs ................................................................................................ 24
3.4 Mixed I/O Systems............................................................................................................. 24
4. Electrical Specifications .......................................................................................................25
4.1 Absolute Maximum Ratings .............................................................................................. 25
4.2 Recommended Operating Conditions ................................................................................ 25
I-Cube, Inc.
[Rev. 1.6] 2/20/01
3