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a
Dual/Quad Low Power, High Speed
JFET Operational Amplifiers
OP282/OP482
FEATURES
High Slew Rate: 9 V/s
Wide Bandwidth: 4 MHz
Low Supply Current: 250 A/Amplifier
Low Offset Voltage: 3 mV
Low Bias Current: 100 pA
Fast Settling Time
Common-Mode Range Includes V+
Unity Gain Stable
APPLICATIONS
Active Filters
Fast Amplifiers
Integrators
Supply Current Monitoring
GENERAL DESCRIPTION
The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. Slew rate
exceeds 7 V/µs with supply current under 250 µA per amplifier.
These unity gain stable amplifiers have a typical gain bandwidth
of 4 MHz.
The JFET input stage of the OP282/OP482 insures bias current
is typically a few picoamps and below 500 pA over the full
temperature range. Offset voltage is under 3 mV for the dual
and under 4 mV for the quad.
With a wide output swing, within 1.5 volts of each supply, low
power consumption and high slew rate, the OP282/OP482 are
ideal for battery-powered systems or power restricted applica-
tions. An input common-mode range that includes the positive
supply makes the OP282/OP482 an excellent choice for high-
side signal conditioning.
The OP282/OP482 are specified over the extended industrial
temperature range. Both dual and quad amplifiers are available
in plastic and ceramic DIP plus SOIC surface mount packages.
PIN CONNECTIONS
8-Lead Narrow-Body SOIC
8-Lead Epoxy DIP
(S Suffix)
(P Suffix)
OUT A 1
–IN A 2
+IN A 3
V– 4
OP282
8 V+
7 OUT B
6 –IN B
5 +IN B
OUT A 1
–IN A 2
+IN A 3
V– 4
OP282
OP-482
8 V+
7 OUT B
6 –IN B
5 +IN B
14-Lead Epoxy DIP
(P Suffix)
14-Lead Narrow-Body SOIC
(S Suffix)
OUT A 1
–IN A 2
+IN A 3
V+ 4
+IN B 5
–IN B 6
OUT B 7
OP482
14 OUT D
13 –IN D
12 +IN D
11 V–
10 +IN C
9 –IN C
8 OUT C
OUT A 1
–IN A 2
+IN A 3
V+ 4
+IN B 5
–IN B 6
OUT B 7
OP482
14 OUT B
13 –IN D
12 +IN D
11 V–
10 +IN C
9 –IN C
8 OUT C
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

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OP282/OP482–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = ؎15.0 V, TA = +25؇C unless otherwise noted)
Parameter
Symbol
Conditions
Min Typ Max Units
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection
Large Signal Voltage Gain
Offset Voltage Drift
Bias Current Drift
VOS
VOS
IB
IOS
CMR
AVO
VOS/T
IB/T
OP282
OP282, –40 TA +85°C
OP482
OP482, –40 TA +85°C
VCM = 0 V
VCM = 0 V, Note 1
VCM = 0 V
VCM = 0 V, Note 1
–11 V VCM +15 V, –40 TA +85°C
RL = 10 k
RL = 10 k, –40 TA +85°C
–11
70
20
15
OUTPUT CHARACTERISTICS
Output Voltage Swing
Short Circuit Limit
Open-Loop Output Impedance
VO
ISC
ZOUT
RL = 10 k
Source
Sink
f = 1 MHz
–13.5
3
–8
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Supply Voltage Range
PSRR
ISY
VS
VS = ± 4.5 V to ± 18 V,
–40 TA +85°C
VO = 0 V, 40 TA +85°C
± 4.5
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
SR
BWP
tS
GBP
ØO
RL = 10 k
1% Distortion
To 0.01%
7
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
NOTE
1The input bias and offset currents are tested at TA = TJ = +85°C. Bias and offset currents are guaranteed but not tested at –40 °C.
Specifications subject to change without notice.
0.2
0.2
3
1
90
10
8
± 13.9
10
–12
200
25
210
9
125
1.6
4
55
1.3
36
0.01
3
4.5
4
6
100
500
50
250
+15
13.5
316
250
± 18
mV
mV
mV
mV
pA
pA
pA
pA
V
dB
V/mV
V/mV
µV/°C
pA/°C
V
mA
mA
µV/V
µA
V
V/µs
kHz
µs
MHz
Degrees
µV p-p
nV/Hz
pA/Hz
WAFER TEST LIMITS (@ VS = ؎15.0 V, TA = +25؇C unless otherwise noted)
Parameter
Symbol
Conditions
Limit
Units
Offset Voltage
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range1
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Range
Supply Current/Amplifier
VOS
VOS
IB
IOS
CMRR
PSRR
AVO
VO
ISY
OP282
OP482
VCM = 0 V
VCM = 0 V
–11 V VCM +15 V
V = ± 4.5 V to ± 18 V
RL = 10 k
RL = 10 k
VO = 0 V, RL =
3
4
100
50
–11, +15
70
316
20
± 13.5
250
mV max
mV max
pA max
pA max
V min/max
dB min
µV/V
V/mV min
V min
µA max
NOTES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
1Guaranteed by CMR test.
Specifications subject to change without notice.
–2– REV. B

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ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Differential Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . 36 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP282A, OP482A . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP282G, OP482G . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . +300°C
Package Type
JA2 JC Units
8-Pin Plastic DIP (P)
103 43 °C/W
8-Pin SOIC (S)
158 43 °C/W
14-Pin Plastic DIP (P)
83
39 °C/W
14-Pin SOIC (S)
120 36 °C/W
NOTES
1For supply voltages less than ± 18 V, the absolute maximum input voltage is
equal to the supply voltage.
2θJA is specified for the worst case conditions, i.e., θJA is specified for device in
socket for cerdip, P-DIP; θJA is specified for device soldered in circuit board for
SOIC package.
Model
OP282GP
OP282GS
OP482GP
OP482GS
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Pin Plastic DIP N-8
8-Pin SOIC
SO-8
14-Pin Plastic DIP N-14
14-Pin SOIC
SO-14
OP282/OP482
DICE CHARACTERISTICS
OP282 Die Size 0.063 ϫ 0.060 Inch, 3,780 Sq. Mils
OP482 Die Size 0.070 ϫ 0.098 Inch, 6,860 Sq. Mils
REV. B
–3–

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OP282/OP482
APPLICATIONS INFORMATION
The OP282 and OP482 are single and dual JFET op amps that
have been optimized for high speed at low power. This
combination makes these amplifiers excellent choices for battery
powered or low power applications requiring above average
performance. Applications benefiting from this performance
combination include telecom, geophysical exploration, portable
medical equipment and navigational instrumentation.
HIGH SIDE SIGNAL CONDITIONING
There are many applications that require the sensing of signals
near the positive rail. OP282s and OP482s have been tested and
guaranteed over a common-mode range (–11 V VCM +15 V)
that includes the positive supply.
One application where this is commonly used is in the sensing of
power supply currents. This enables it to be used in current
sensing applications such as the partial circuit shown in Figure
1. In this circuit, the voltage drop across a low value resistor,
such as the 0.1 shown here, is amplified and compared to 7.5
volts. The output can then be used for current limiting.
+15V
0.1
100k
100k
500k
RL
+ 1/2
OP282
100k
Figure 1. Phase Inversion
PHASE INVERSION
Most JFET-input amplifiers will invert the phase of the input
signal if either input exceeds the input common-mode range.
For the OP282 and OP482 negative signals in excess of approxi-
mately 14 volts will cause phase inversion. The cause of this
effect is saturation of the input stage leading to the forward-
biasing of a drain-gate diode. A simple fix for this in noninverting
applications is to place a resistor in series with the noninverting
input. This limits the amount of current through the forward-
biased diode and prevents the shutting down of the output
stage. For the OP282/OP482, a value of 200 khas been found
to work. However, this adds a significant amount of noise.
15
10
5
0
-5
-10
-15
-15
-10
-5 0
5
VOUT
10
Figure 2. OP282 Phase Reversal
15
ACTIVE FILTERS
The OP282 and OP482’s wide bandwidth and high slew rates
make either an excellent choice for many filter applications.
There are many types of active filter configurations, but the four
most popular configurations are Butterworth, elliptical, Bessel,
and Chebyshev. Each type has a response that is optimized for a
given characteristic as shown in Table I.
PROGRAMMABLE STATE-VARIABLE FILTER
Type
Butterworth
Chebyshev
Elliptical
Bessel (Thompson)
Table I.
Selectivity Overshoot Phase
Amplitude
(Pass Band)
Moderate
Good
Best
Poor
Good
Moderate
Poor
Best
Nonlinear
Linear
Max Flat
Equal Ripple
Equal Ripple
Amplitude
(Stop Band)
Equal Ripple
–4– REV. B

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The circuit shown in Figure 3 can be used to accurately
program the “Q,” the cutoff frequency fC, and the gain of a two
pole state-variable filter. OP482s have been used in this design
because of their high bandwidths, low power and low noise.
This circuit takes only three packages to build because of the
quad configuration of the op amps and DACs.
The DACs shown are all used in the voltage mode so all values
are dependent only on the accuracy of the DAC and not on the
absolute values of the DAC’s resistive ladders. This make this
circuit unusually accurate for a programmable filter.
Adjusting DAC 1 changes the signal amplitude across R1;
therefore, the DAC attenuation times R1 determines the
amount of signal current that charges the integrating capacitor,
C1. This cutoff frequency can now be expressed as:
OP282/OP482
fc
=
1
2πR1C1

D1
256

where D1 is the digital code for the DAC.
Gain of this circuit is set by adjusting D3. The gain equation is:
Gain
=
R4
R5

D3
256

DAC 2 is used to set the “Q” of the circuit. Adjusting this DAC
controls the amount of feedback from the bandpass node to the
input summing node. Note that the digital value of the DAC is
in the numerator, therefore zero code is not a valid operating point.
Q
=
R2
R3
256
 D2 
1/4
DAC8408
VIN
-
+
1/4
OP482
R5
2k
R7
2k
R4
2k 1/4
DAC8408
-
+
1/4
OP482
HIGH PASS
-
+
1/4
OP482
R1
2k
C1
1000pF
1/4
DAC8408
-
+
1/4
OP482
C1
1000pF
R1
- 2k
+
1/4
OP482
-
+ LOW
1/4 PASS
OP482
R6
2k 1/4
R3 DAC8408
2k
R2
BANDPASS
-
+
1/4
OP482
1k -
+
1/4
OP482
Figure 3.
REV. B
–5–