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SN74LS273
Octal D Flip-Flop
with Clear
The SN74LS273 is a high-speed 8-Bit Register. The register
consists of eight D-Type Flip-Flops with a Common Clock and an
asynchronous active LOW Master Reset. This device is supplied in a
20-pin package featuring 0.3 inch lead spacing.
8-Bit High Speed Register
Parallel Register
Common Clock and Master Reset
Input Clamp Diodes Limit High-Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current – High
IOL Output Current – Low
– 0.4
8.0
mA
mA
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LOW
POWER
SCHOTTKY
20
1
PLASTIC
N SUFFIX
CASE 738
20
1
SOIC
DW SUFFIX
CASE 751D
ORDERING INFORMATION
Device
Package
Shipping
SN74LS273N 16 Pin DIP 1440 Units/Box
SN74LS273DW 16 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1
Publication Order Number:
SN74LS273/D

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SN74LS273
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
PIN NAMES
CP
D0 – D7
MR
Q0 – Q7
Clock (Active HIGH Going Edge) Input
Data Inputs
Master Reset (Active LOW) Input
Register Outputs
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
TRUTH TABLE
MR CP
LX
H
H
Dx
X
H
L
Qx
L
H
L
H = HIGH Logic Level
L = LOW Logic Level
X = Immaterial
3
11 D0
CP
CP D
1 CD Q
MR
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
Q0
2
4
D1
CP D
CD Q
Q1
5
LOGIC DIAGRAM
78
D2 D3
13
D4
CP D
CD Q
CP D
CD Q
CP D
CD Q
Q2 Q3 Q4
6 9 12
14
D5
CP D
CD Q
Q5
15
17
D6
CP D
CD Q
Q6
16
18
D7
CP D
CD Q
Q7
19
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SN74LS273
FUNCTIONAL DESCRIPTION
The SN74LS273 is an 8-Bit Parallel Register with a
common Clock and common Master Reset.
When the MR input is LOW, the Q outputs are LOW,
independent of the other inputs. Information meeting the
setup and hold time requirements of the D inputs is
transferred to the Q outputs on the LOW-to-HIGH transition
of the clock input.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
Guaranteed Input HIGH Voltage for
V All Inputs
VIL Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
VOH
VOL
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
2.7 3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
0.25 0.4
0.35 0.5
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IIH Input HIGH Current
20 µA
0.1 mA
IIL Input LOW Current
– 0.4 mA
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA
ICC Power Supply Current
27 mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol
fMAX
tPHL
tPLH
tPHL
Parameter
Maximum Input Clock Frequency
Propagation Delay, MR to Q Output
Min
30
Propagation Delay, Clock to Output
Limits
Typ
40
18
17
18
Max
27
27
27
Unit
MHz
ns
ns
Test Conditions
Figure 1
Figure 2
Figure 1
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
tw
ts
th
trec
Parameter
Pulse Width, Clock or Clear
Data Setup Time
Hold Time
Recovery Time
Min
20
20
5.0
25
Limits
Typ
Max
Unit
ns
ns
ns
ns
Test Conditions
Figure 1
Figure 1
Figure 1
Figure 2
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SN74LS273
AC WAVEFORMS
1/f max
tW
CP 1.3 V 1.3 V 1.3 V 1.3 V
ts(H) th(H) ts(L) th(L)
D*
1.3 V
1.3 V 1.3 V
tPLH tPHL
Qn 1.3 V 1.3 V
tPHL tPLH
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW-to-HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the clock transition from LOW-to-HIGH that the
logic level must be maintained at the input in order to ensure
MR
tW
1.3 V
CP
Qn
tPLH
Qn
tPHL
1.3 V
1.3 V
trec
1.3 V
1.3 V
1.3 V
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
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–A–
20
1
–T–
SEATING
PLANE
E
GF
SN74LS273
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
11
B
10
C
K
N
D 20 PL
0.25 (0.010) M T A M
L
M
J 20 PL
0.25 (0.010) M
TBM
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 1.010 1.070 25.66 27.17
B 0.240 0.260 6.10 6.60
C 0.150 0.180 3.81 4.57
D 0.015 0.022 0.39 0.55
E 0.050 BSC
1.27 BSC
F 0.050 0.070 1.27 1.77
G 0.100 BSC
2.54 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.140 2.80 3.55
L 0.300 BSC
7.62 BSC
M 0_ 15_ 0_ 15_
N 0.020 0.040 0.51 1.01
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