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® NOT RDEPaCLtOaEMASSMhEeEeNRtDEEFEDRFOTOR INSELW644D1ESIDGeNcSember 1, 2004
ISL6402A
FN9010.3
1.4MHz Dual, 180° Out-of-Phase, Step-
Down PWM and Single Linear Controller
The ISL6402A is a high-performance, triple-output controller
optimized for converting wall adapter, battery or network
intermediate bus DC input supplies into the system supply
voltages required for a wide variety of applications. Each
output is adjustable down to 0.8V. The two PWMs are
synchronized 180o out of phase reducing the RMS input
current and ripple voltage.
The ISL6402A incorporates several protection features. An
adjustable overcurrent protection circuit monitors the output
current by sensing the voltage drop across the lower
MOSFET. Hiccup mode overcurrent operation protects the
DC-DC components from damage during output
overload/short circuit conditions. Each PWM has an
independent logic-level shutdown input (SD1 and SD2).
A single PGOOD signal is issued when soft-start is complete
on both PWM controllers and their outputs are within 10% of
the set point and the linear regulator output is greater than
75% of its setpoint. Thermal shutdown circuitry turns off the
device if the junction temperature exceeds +150°C.
Ordering Information
TEMP. RANGE
PART NUMBER
(°C)
PACKAGE
PKG.
DWG. #
ISL6402AIR
-40 to 85 28 Ld QFN L28.5x5
ISL6402AIR-T
28 Ld QFN Tape and Reel
L28.5x5
ISL6402AIR-TK 28 Ld QFN Tape and Reel
L28.5x5
ISL6402AIRZ
(See Note)
-40 to 85
28 Ld QFN
(Pb-free)
L28.5x5
ISL6402AIRZ-T
(See Note)
28 Ld QFN Tape and Reel
(Pb-free)
L28.5x5
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
Features
• Wide Input Supply Voltage Range . . . . . . . . . 4.5V to 24V
• Three Independently Programmable Output Voltages
• Switching Frequency . . . . . . . . . . . . . . . . . . . . . . .1.4MHz
• Out of Phase PWM Controller Operation
- Reduces Required Input Capacitance and Power
Supply Induced Loads
• No External Current Sense Resistor
- Uses Lower MOSFET’s rDS(ON)
• Bi-directional Frequency Synchronization for
Synchronizing Multiple ISL6402As
• Programmable Soft-Start
• Extensive circuit protection functions
- PGOOD
- UVLO
- Overcurrent
- Overtemperature
- Independent Shutdown for Both PWMs
• Excellent Dynamic Response
- Voltage Feed-Forward with Current Mode Control
• QFN Packages:
- QFN - Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Available (RoHS Compliant)
Applications
• Power Supplies with Multiple Outputs
• xDSL Modems/Routers
• DSP, ASIC, and FPGA Power Supplies
• Set-Top Boxes
• Dual Output Supplies for DSP, Memory, Logic, µP Core
and I/O
• Telecom Systems
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinout
ISL6402A
ISL6402A (QFN)
TOP VIEW
28 27 26 25 24 23 22
PHASE2 1
21 ISEN1
ISEN2 2
20 PGND
PGOOD 3
19 SD1
VCC_5V 4
18 SS1
SD2 5
17 SGND
SS2 6
16 OCSET1
OCSET2 7
15 FB1
8 9 10 11 12 13 14
2 FN9010.3

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Block Diagram
SGND VCC_5V
VIN SYNC
PGOOD
FB3 GATE3
LDO &
SS1
SS1
POWER-ON
RESET (POR)
SS2
SS2 POR +5V
RAMP
BOOT1
UGATE1
PHASE1
HGDR
VCC_5V
HI
GATE LOGIC
PWM1
SHUTDOWN SD1
LGATE1
PGND
LGDR
LO
PWM
SD1
FB1
OCSET1
-
REF
ISEN1
-
-
OC
COMP
CLOCK
CLK
FB1 OUTPUT
VOLTAGE
FB2 MONITOR
FB3
LINEAR
CONTROLLER
REF
HI
GATE LOGIC
PWM2
SD2 SHUTDOWN
HGDR
BOOT2
UGATE2
PHASE2
VCC_5V
PWM
LGDR
LO
LGATE2
OC SS1
LOGIC
SS2 OC
LOGIC
- SQ
CLK
R
PWM1
LATCH
QS
CLK
R
PWM2
LATCH
-
-
OC
COMP
SD2
-
REF
FB2
OCSET2
ISEN2
-

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Typical Application Schematic
ISL6402A
+ C1
+12V
D1
C2
C7
VOUT1
+1.2V
R1
L1
+ C9
R2
SD1
C4
GATE3
ISEN1 21 13
C3
BOOT2 27
Q1A
LGATE2 26
LGATE1 25
R3 BOOT1 24
OCSET2
7 9 SGND
C5
2 ISEN2
Q1A
3 PGOOD
4 VCC_5V
5 SD2
R4
Q1B
UGATE2 28
UGATE1 23
ISL6402A
(See Note)
Q2B
1 PHASE2
11 SYNC
SS1 18
PHASE1 22
FB2 8
SD1
19
R7 20 14
PGND
SGND
12 FB3
17 SGND
16 OCSET1
FB1
15
VIN
10
6 R10
SS2
R8 R9
VCC_5V
D2
C6
C8
L2
C10 +
VOUT2
+3.3V
R5
R6
C11 VOUT2
+3.3V
R11
R12
Q3
VOUT3
+2.5V
+ C12
R13
NOTE: Pin numbers correspond to the QFN pinout.
4 FN9010.3

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ISL6402A
Absolute Maximum Ratings
Supply Voltage (VCC_5V Pin) . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Input Voltage (VIN Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+30V
BOOT1, 2 and UGATE1, 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . +35V
PHASE1, 2 and ISEN1, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30V
BOOT1, 2 with respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . . +6.5V
UGATE1, 2. . . . . . . . . . . . (PHASE1, 2 - 0.3V) to (BOOT1, 2 +0.3V)
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
28 Lead QFN (Note 2) . . . . . . . . . . .
33
4
Maximum Junction Temperature (Plastic Package) . -55°C to 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJC is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. For θJA
the “case temp” location is the center of the exposed metal pad on the underside of the package. See Tech Brief TB379.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
Schematic. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to 85°C (Note 3),
Typical values are at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIN SUPPLY
Input Voltage Range
5.6 12
24
V
VCC_5V SUPPLY (Note 4)
Input Voltage
4.5 5.0 5.6
V
Output Voltage
Maximum Output Current
SUPPLY CURRENT
VIN > 5.6V, IL = 20mA
VIN = 12V
4.5 5.0 5.5
V
60 -
- mA
Shutdown Current (Note 5)
SD1 = SD2 = GND
- 50 375 µA
Operating Current (Note 6)
- 2.0 4.0 mA
REFERENCE SECTION
Nominal Reference Voltage
- 0.8 -
V
Reference Voltage Tolerance
-1.0 - 1.0 %
POWER-ON RESET
Rising VCC_5V Threshold
4.25 4.45
4.5
V
Falling VCC_5V Threshold
3.95 4.2
4.4
V
OSCILLATOR
Total Frequency Variation
1.25 1.4
1.5 MHz
Peak-to-Peak Sawtooth Amplitude (Note 7)
Ramp Offset (Note 8)
VIN = 12V
VIN = 5V
- 1.5 -
- 0.625 -
- 1.0 -
V
V
V
SYNC Input Rise/Fall Time
- - 10.0 ns
SYNC Frequency Range
5.1 5.6 6.0 MHz
SYNC Input HIGH Level
3.5 - - V
SYNC Input LOW Level
- - 1.5 V
SYNC Input Minimum Pulse Width
10 -
- ns
SYNC Output HIGH Level
VCC - 0.6V
-
-
V
5 FN9010.3