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AT27C4096
Features
Fast Read Access Time - 55 ns
Low Power CMOS Operation
– 100 µA Maximum Standby
– 40 mA Maximum Active at 5 MHz
JEDEC Standard Packages
– 40-Lead 600 mil PDIP
– 44-Lead PLCC
– 40-Lead TSOP (10 mm x 14 mm)
Direct Upgrade from 512K bit, 1M bit, and 2M bit
(AT27C516, AT27C1024, and AT27C2048) EPROMs
5V ± 10% Power Supply
High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
RapidProgramming Algorithm - 50 µs/word (typical)
CMOS and TTL Compatible Inputs and Outputs
Integrated Product Identification Code
Commercial and Industrial Temperature Ranges
Description
The AT27C4096 is a low-power, high-performance 4,194,304-bit one-time program-
mable read only memory (OTP EPROM) organized 256K by 16 bits. It requires a sin-
gle 5V power supply in normal read mode operation. Any word can be accessed in
less than 55 ns, eliminating the need for speed-reducing WAIT states. The by-16
organization makes this part ideal for high-performance 16- and 32-bit microprocessor
systems.
Pin Configurations
PDIP Top View
(continued)
Pin Name Function
A0 - A17 Addresses
O0 - O15 Outputs
CE Chip Enable
OE Output Enable
NC
Note:
No Connect
Both GND pins must be
connected.
4-Megabit
(256K x 16)
OTP EPROM
AT27C4096
PLCC Top View
TSOP Top View
Type 1
0311E-A–06/97
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Description
In read mode, the AT27C4096 typically consumes 15 mA.
Standby mode supply current is typically less than 10 µA.
The AT27C4096 is available in industry standard
JEDEC-approved one-time programmable (OTP) plastic
PDIP, PLCC, and TSOP packages. The device features
two-line control (CE, OE) to eliminate bus contention in
high-speed systems.
With high density 256K word storage capability, the
AT27C4096 allows firmware to be stored reliably and to be
accessed by the system without the delays of mass storage
media.
Atmel’s AT27C4096 has additional features that ensure
high quality and efficient production use. The RapidPro-
gramming Algorithm reduces the time required to program
the part and guarantees reliable programming. Program-
ming time is typically only 50 µs/word. The Integrated Prod-
uct Identification Code electronically identifies the device
and manufacturer. This feature is used by industry stan-
dard programming equipment to select the proper program-
ming algorithms and voltages.
System Considerations
Switching between active and standby conditions via the
Chip Enable pin may produce transient voltage excursions.
Unless accommodated by the system design, these tran-
sients may exceed data sheet limits, resulting in device
non-conformance. At a minimum, a 0.1 µF high frequency,
low inherent inductance, ceramic capacitor should be uti-
lized for each device. This capacitor should be connected
between the VCC and Ground terminals of the device, as
close to the device as possible. Additionally, to stabilize the
supply voltage level on printed circuit boards with large
EPROM arrays, a 4.7 µF bulk electrolytic capacitor should
be utilized, again connected between the VCC and Ground
terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected
to the array.
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Block Diagram
AT27C4096
Absolute Maximum Ratings*
Temperature Under Bias ......................-55°C to +125°C
Storage Temperature............................-65°C to +150°C
Voltage on Any Pin with
Respect to Ground ...............................-2.0V to +7.0V(1)
Voltage on A9 with
Respect to Ground ............................-2.0V to +14.0V(1)
VPP Supply Voltage with
Respect to Ground .............................-2.0V to +14.0V(1)
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
Maximum voltage is -0.6V dc which may undershoot
to -2.0V for pulses of less than 20 ns. Maximum out-
put pin voltage is VCC + 0.75V dc which may over-
shoot to +7.0V for pulses of less than 20 ns.
Operating Modes
Mode/Pin
Read
CE OE Ai VPP Outputs
VIL VIL Ai X(1) DOUT
Output Disable
Standby
Rapid Program(2)
X VIH
VIH X
X
X
X High Z
X(5) High Z
VIL VIH Ai VPP DIN
PGM Verify
VIH VIL
Ai VPP DOUT
PGM Inhibit
Product Identification(4)
Notes: 1. X can be VIL or VIH.
2. Refer to the Programming characteristics.
VIH VIH X VPP High Z
A9 = VH(3)
VIL VIL A0 = VIH or VIL VCC Identification Code
A1 - A17 = VIL
3. VH = 12.0 ± 0.5V.
4. Two identifier words may be selected. All Ai inputs are held low (VIL), except A9, which is set to VH, and A0, which is toggled
low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word.
5. Standby VCC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB.
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DC and AC Operating Conditions for Read Operation
Operating Temperature
(Case)
VCC Power Supply
Com.
Ind.
-55
0°C - 70°C
-40°C - 85°C
5V ± 10%
-70
0°C - 70°C
-40°C - 85°C
5V ± 10%
AT27C4096
-90
0°C - 70°C
-40°C - 85°C
5V ± 10%
-12
0°C - 70°C
-40°C - 85°C
5V ± 10%
-15
0°C - 70°C
-40°C - 85°C
5V ± 10%
DC and Operating Characteristics for Read Operation
Symbol Parameter
Condition
Min Max Units
ILI Input Load Current
VIN = 0V to VCC
± 1 µA
ILO
IPP1(2)
Output Leakage Current
VPP(1) Read/Standby Current
VOUT = 0V to VCC
VPP = VCC
± 5 µA
10 µA
ISB VCC(1) Standby Current
ISB1 (CMOS)
CE = VCC ± 0.3V
ISB2 (TTL)
CE = 2.0 to VCC + 0.5V
100 µA
1 mA
ICC VCC Active Current
f = 5 MHz, IOUT = 0 mA,
CE = VIL
40 mA
VIL Input Low Voltage
-0.6 0.8 V
VIH Input High Voltage
2.0
VCC + 0.5
V
VOL Output Low Voltage
IOL = 2.1 mA
0.4 V
VOH
Notes:
Output High Voltage
IOH = -400 µA
2.4 V
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and
IPP.
AC Characteristics for Read Operation
-55 -70
Symbol Parameter
Condition
Min Max Min Max
tACC(3)
tCE(2)
tOE(2)(3)
tDF(4)(5)
Address to
Output Delay
CE to Output Delay
OE to Output Delay
OE or CE High to
Output Float,
whichever occurred
first
CE = OE
= VIL
OE = VIL
CE = VIL
55 70
55 70
20 30
20 20
tOH(4)
Output Hold from
Address, CE or OE,
whichever occurred
first
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Note: 2, 3, 4, 5. See the AC Waveforms for Read Operation diagram.
AT27C4096
-90
Min Max
90
90
35
20
0
-12
Min Max
120
120
40
30
0
-15
Min Max
150
150
50
35
0
Units
ns
ns
ns
ns
ns
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AC Waveforms for Read Operation(1)
AT27C4096
Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
Input Test Waveforms and Measurement Levels
For -55 devices only:
Output Test Load
tR, tF < 5 ns (10% to 90%)
For -70, -90, -12 and -15 devices:
Note:
CL = 100 pF including jig
capacitance, except for
the -45 and -55 devices,
where CL = 30 pF.
tR, tF < 20 ns (10% to 90%)
Pin Capacitance
(f = 1 MHz T = 25°C)(1)
Typ Max Units
Conditions
CIN
4 10 pF
VIN = 0V
COUT
8 12 pF
VOUT = 0V
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
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