Embedded Ultra-Low Power Intel486™ GX Processor
This data sheet describes the embedded Ultra-Low
Power (ULP) Intel486™ GX processor. It is intended
for embedded battery-operated and hand-held appli-
cations. The embedded ULP Intel486 GX processor
provides all of the features of the Intel486 SX
processor except for the 8-bit bus sizing logic and
the processor-upgrade pin. The processor typically
uses 20% to 50% less power than the Intel486 SX
processor. Additionally, the embedded ULP Intel486
GX processor external data bus and parity signals
have level-keeper circuitry and a fast-recovery core
clock which are vital for ultra-low-power system
designs. The processor is available in a Thin Quad
Flat Package (TQFP) enabling low-profile
The embedded ULP Intel486 GX processor consists
of a 32-bit integer processing unit, an on-chip cache,
and a memory management unit. The design
ensures full instruction-set compatibility with the
8086, 8088, 80186, 80286, Intel386™ SX, Intel386
DX, and all versions of Intel486 processors.
The embedded ULP Intel486 GX processor offers
these features of the Intel486 SX processor:
• 32-bit RISC-Technology Core — The embedded
ULP Intel486 GX processor performs a complete
set of arithmetic and logical operations on 8-, 16-,
and 32-bit data types using a full-width ALU and
eight general purpose registers.
• Single Cycle Execution — Many instructions
execute in a single clock cycle.
• Instruction Pipelining — Overlapped instruction
fetching, decoding, address translation and
• On-Chip Cache with Cache Consistency
Support — An 8-Kbyte, write-through, internal
cache is used for both data and instructions.
Cache hits provide zero wait-state access times
for data within the cache. Bus activity is tracked to
detect alterations in the memory represented by
the internal cache. The internal cache can be
invalidated or flushed so that an external cache
controller can maintain cache consistency.
• External Cache Control — Write-back and flush
controls for an external cache are provided so the
processor can maintain cache consistency.
• On-Chip Memory Management Unit — Address
management and memory space protection
mechanisms maintain the integrity of memory in a
multitasking and virtual memory environment. Both
segmentation and paging are supported.
• Burst Cycles — Burst transfers allow a new 16-bit
data word to be read from memory on each bus
clock cycle. This capability is especially useful for
instruction prefetch and for filling the internal
cache. Burst transfers also occur on some
memory write and some I/O data transfers.
• Write Buffers — The processor contains four
write buffers to enhance the performance of
consecutive writes to memory. The processor can
continue internal operations after a write to these
buffers, without waiting for the write to be
completed on the external bus.
• Bus Backoff — When another bus master needs
control of the bus during a processor initiated bus
cycle, the embedded ULP Intel486 GX processor
floats its bus signals, then restarts the cycle when
the bus becomes available again.
• Instruction Restart — Programs can continue
execution following an exception generated by an
unsuccessful attempt to access memory. This
feature is important for supporting demand-paged
virtual memory applications.
• Boundary Scan (JTAG) — Boundary Scan
provides in-circuit testing of components on
printed circuit boards. The Intel Boundary Scan
implementation conforms with the IEEE Standard
Test Access Port and Boundary Scan Architecture.