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19-1207; Rev 1; 7/04
EVAALVUAAILTAIOBNLEKIT
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________General Description
The MAX3691 serializer is ideal for converting 4-bit-
wide, 155Mbps parallel data to 622Mbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts low-voltage
differential-signal (LVDS) clock and data inputs for
interfacing with high-speed digital circuitry, and deliv-
ers a 3.3V PECL serial-data output. A fully integrated
PLL synthesizes an internal 622Mbps serial clock from
a 155.52MHz reference clock.
The MAX3691 is available in the extended-industrial
temperature range (-40°C to +85°C), in a 32-pin TQFP
package.
________________________Applications
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
____________________________Features
Single +3.3V Supply
155Mbps Parallel to 622Mbps Serial Conversion
215mW Power
LVDS Parallel Clock and Data Inputs
Differential 3.3V PECL Serial-Data Output
______________Ordering Information
PART
TEMP RANGE
MAX3691ECJ
-40°C to +85°C
MAX3691ECJ+ -40°C to +85°C
+Denotes lead-free package.
PIN-PACKAGE
32 TQFP
32 TQFP
Pin Configuration appears at end of data sheet.
___________________________________________________Typical Operating Circuit
LVDS CRYSTAL REFERENCE
0.1µF
0.1µF
OVERHEAD
GENERATION
VCC = +3.3V
PCLKI- PCLKI+ RCLK- RCLK+
PD0+
PD0-
VCC GND
FIL+
PD1+
PD1- MAX3691
PD2+
PD2-
PD3+
FIL-
PD3-
PCLKO- PCLKO+
SD- SD+
1.5k
100pF
VCC = +3.3V
130
24.9k
130
VCC = +3.3V
MAX3668
THIS SYMBOL REPRESENTS A TRANSMISSION LINE
OF CHARACTERISTIC IMPEDANCE (Z0 = 50)
8282
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

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+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
VCC .........................................................................-0.5V to 5V
All Inputs.................................................-0.5V to (VCC + 0.5V)
Output Current
LVDS Outputs (PCLKO±)................................................10mA
PECL Outputs (SD±).......................................................50mA
Continuous Power Dissipation (TA = +85°C)
TQFP (derate 10.20mW/°C above +85°C) ...................663mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential LVDS loads = 100±1%, PECL loads = 50±1% to (VCC - 2V), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Supply Current
ICC PECL outputs unterminated 38
65 100
PECL OUTPUTS (SD±)
Output High Voltage
VOH
TA = +25°C to +85°C
TA = -40°C
VCC - 1.03
VCC - 1.08
VCC - 0.88
VCC - 0.88
Output Low Voltage
VOL
TA = +25°C to +85°C
TA = -40°C
VCC - 1.81
VCC - 1.95
VCC - 1.62
VCC - 1.62
LVDS INPUTS AND OUTPUTS (PCLKI±, RCLK±, PCLKO±, PD_±)
UNITS
mA
V
V
Input Voltage Range
VI
Differential input voltage =
100mV
0
2.4 V
Differential Input Threshold
VIDTH
Common-mode voltage =
50mV
-100
100 mV
Threshold Hysteresis
Differential Input Resistance
Output High Voltage
Output Low Voltage
Differential Output Voltage
Change in Magnitude of Differential Output
Voltage for Complementary States
VHYST
RIN
VOH
VOL
VOD
VOD
70
85 100 115
1.475
0.925
250 400
25
mV
V
V
mV
mV
Output Offset Voltage
Change in Magnitude of Output Offset Voltage
for Complementary States
Single-Ended Output Resistance
Change in Magnitude of Single-Ended Output
Resistance for Complementary States
VOS
VOS
RO
RO
TA = +25°C
1.125
1.275
25
40 70 140
±1 ±10
V
mV
%
2 _______________________________________________________________________________________

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+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential LVDS load = 100±1%, PECL loads = 50±1% to (VCC - 2V) TA = +25°C, unless otherwise
noted. Typical values are at VCC = +3.3V.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Serial Clock Rate
Parallel Data-Setup Time
Parallel Data-Hold Time
fSCLK
tSU
tH
622.08
200
600
MHz
ps
ps
PCLKO to PCLKI Skew
tSKEW
-0.7
+3.3
ns
Output Jitter
Φ0 TA = -40°C to +85°C (Note 2)
PECL Differential Output
Rise/Fall Time
tR, tF
Note 1: AC characteristics guaranteed by design and characterization.
Note 2: Assumes a 50% duty cycle ±5%.
13 psRMS
400 ps
__________________________________________Typical Operating Characteristics
(VCC = +3.0V to +3.6V, differential LVDS loads = 100, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
100
PARALLEL DATA-SETUP TIME
vs. TEMPERATURE
-20
80 -40
60 -60
40 -80
20 -100
0
-50 -25 0 25 50 75 100
TEMPERATURE (°C)
-120
-50 -25 0 25 50 75 100
TEMPERATURE (°C)
PARALLEL DATA-HOLD TIME
vs. TEMPERATURE
250
230
210
190
170
150
-50 -25 0 25 50 75 100
TEMPERATURE (°C)
_______________________________________________________________________________________ 3

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+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
____________________________Typical Operating Characteristics (continued)
(VCC = +3.0V to +3.6V, differential LVDS loads = 100, unless otherwise noted.)
PCLKO-to-PCLKI SKEW
vs. TEMPERATURE
6
SERIAL-DATA OUTPUT EYE DIAGRAM
(622Mbps, 27-1 PRBS)
1.21V
908mV
SERIAL-DATA OUTPUT JITTER
4
OC-12
SONET MASK
2 10mV/
div
62mV/
0 div
fRCLK = 155.52MHz
-2
-4 0.59V
-50 -25 0 25 50 75 100
TEMPERATURE (°C)
161ps/div
808mV
Mean 23.88ns
RMS8.418ps
PkPk 70.2ps
10ps/div
µ±1σ 68.774%
µ±2σ 95.534%
µ±3σ 99.738%
______________________________________________________________Pin Description
PIN NAME
1, 3, 5, 7 PD0+ to PD3+
2, 4, 6, 8 PD0- to PD3-
9, 17, 18,
19, 24,
25, 32
GND
10 PCLKO-
11 PCLKO+
12, 13, 16,
20, 21,
28, 29
VCC
14 SD-
15 SD+
FUNCTION
Noninverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
Inverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
Ground
Inverting LVDS Parallel-Clock Output. Use PCLKO to clock the overhead management circuit.
Noninverting LVDS Parallel-Clock Output. Use PCLKO to clock the overhead management circuit.
+3.3V Supply Voltage
Inverting PECL Serial-Data Output
Noninverting PECL Serial-Data Output
22 FIL- Filter Capacitor Input. See Typical Operating Circuit for external-component connections.
23
FIL+
Filter Capacitor Input. See Typical Operating Circuit for external-component connections.
26
RCLK+
Noninverting LVDS Reference Clock Input. Connect (AC couple) a crystal reference clock
(155.52MHz) to the RCLK inputs.
27
RCLK-
Inverting LVDS Reference Clock Input. Connect (AC couple) a crystal reference clock (155.52MHz)
to the RCLK inputs.
30
PCLKI+
Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the
PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.
31
PCLKI-
Inverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI
inputs. Note that data is updated on the positive transition of the PCLKI signal.
4 _______________________________________________________________________________________

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+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________Detailed Description
The MAX3691 serializer comprises a 4-bit parallel input
register, a 4-bit shift register, control and timing logic, a
PECL output buffer, LVDS input/output buffers, and a
frequency-synthesizing PLL (consisting of a phase/
frequency detector, loop filter/amplifier, and voltage-
controlled oscillator). This device converts 4-bit-wide,
155Mbps data to 622Mbps serial data (Figure 1).
The PLL synthesizes an internal 622Mbps reference
used to clock the output shift register. This clock is
generated by locking onto the external 155.52MHz
reference-clock signal (RCLK).
The incoming parallel data is clocked into the
MAX3691 on the rising transition of the parallel-clock-
input signal (PCLKI). The control and timing logic
ensure proper operation if the parallel-input register is
latched within a window of time that is defined with
respect to the parallel-clock-output signal (PCLKO).
PCLKO is the synthesized 622Mbps internal serial-
clock signal divided by four. The allowable PCLKO-to-
PCLKI skew is -0.7ns to +3.3ns. This defines a timing
window at about the PCLKO rising edge, during which
a PCLKI rising edge may occur. Figure 2 is the timing
diagram.
PD3+
PD3-
PD2+
PD2-
PD1+
PD1-
PD0+
PD0-
PCLKI+
PCLKI-
RCLK+
RCLK-
LVDS
LVDS
LVDS
4-BIT
PARALLEL
INPUT
REGISTER
LVDS
LVDS
LVDS
PHASE/FREQ
DETECT
MAX3691
SHIFT
4-BIT
SHIFT
SD+
PECL
REGISTER
VCO
CONTROL
LATCH
SD-
LVDS
Figure 1. Functional Diagram
FIL+ FIL-
PCLKO+ PCLKO-
_______________________________________________________________________________________ 5