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19-1534; Rev 1; 10/99
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
General Description
The MAX3831/MAX3832 are 4:1 multiplexers (muxes)
and 1:4 demultiplexers (demuxes) with automatic chan-
nel assignment. Operating from a single +3.3V supply,
the mux receives four parallel, 622Mbps SDH/SONET
channels. These channels are bit interleaved to gener-
ate a serial data stream of 2.488Gbps for interfacing to
an optical or an electrical driver. A 10-bit-wide elastic
buffer tolerates up to ±7.5ns skew between any parallel
data input and the reference clock. An external
155MHz reference clock is required for the on-chip PLL
to synthesize a high-frequency 2.488GHz clock for tim-
ing the outgoing data streams.
The MAX3831/MAX3832’s demux receives 2.488Gbps
serial data and the 2.488GHz clock from an external
clock/data recovery device (MAX3876), converting it to
four 622Mbps LVDS outputs. The MAX3831 provides a
622MHz LVDS clock output, and the MAX3832 pro-
vides a 155MHz LVDS clock output. An internal frame
detector looks for a 622Mbps SDH/SONET framing pat-
tern and rolls the demux to maintain proper channel
assignment at the outputs.
These devices also include an embedded pattern gen-
erator that enables a full-speed, built-in self-test (BIST).
Two different loopback modes provide system test flexi-
bility. A TTL loss-of-frame monitor is included. The
MAX3831/MAX3832 are available in 64-pin TQFP-EP
(exposed paddle) packages and are specified over the
upper commercial (0°C to +85°C) temperature range.
Pin Configuration appears at end of data sheet.
Features
o +3.3V Single Supply
o 1.45W Power Dissipation (MAX3831)
o 4-Channel Mux/Demux with Fully Integrated
2.488GHz Clock Generator
o Frame Detection Maintains Channel Assignment
o ±7.5ns Elastic Store Range
o 2.5ps RMS Serial-Data Output Random Jitter
o 8ps Serial-Data Output Deterministic Jitter
o 622Mbps LVDS Parallel Input/Output
o 2.488Gbps Serial CML Input/Output
o On-Chip Pattern Generator Provides
High-Speed BIST
o System Test Flexibility: System Loopback,
Line Loopback
o Loss-of-Frame Indicator
SDH/SONET Backplanes
High-Speed Parallel Links
Intrarack/Subrack
Interconnects
Applications
ATM Switching Networks
Line Extenders
Dense Digital Cross-
Connects
PART
MAX3831UCB
MAX3832UCB
Ordering Information
TEMP. RANGE
0°C to +85°C
0°C to +85°C
PIN-PACKAGE
64 TQFP-EP
64 TQFP-EP
Typical Application Circuit
155MHz REF
CLOCK INPUT
LVDS
4
4 LVDS
CMOS
OVERHEAD
4
LVDS 4
LVDS
TTL
0.33µF
TTL TTL
+3.3V
TTL
RSETES FIL+ FIL- TEST LOF
RCLKI+
RCLKI-
PDI1+ TO PDI4+
PDI1- TO PDI4-
PDO1+ TO PDO4+
MAX3831
MAX3832
PDO1- TO PDO4-
PCLKO+
PCLKO-
TRIEN GND
PLBEN VCC
SCLKI-
SCLKI+
SDI-
SDI+
SDO+
SDO-
LBEN
RSETFR
0.1µF
CML
MAX3876
2.5Gbps
CML CDR
TTL
TTL
2.5Gbps
OPTICAL
TRANSCEIVER
TTL
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.

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+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (VCC)...............................-0.5V to +5.0V
Input Voltage (LVDS, TTL)..........................-0.5V to (VCC + 0.5V)
CML Input Voltage ..........................(VCC - 0.8V) to (VCC + 0.5V)
FIL+, FIL- Voltage.......................................-0.5V to (VCC + 0.5V)
TTL Output Voltage ....................................-0.5V to (VCC + 0.5V)
LVDS Output Voltage ..................................-0.5V to (VCC +0.5V)
CML Output Currents..........................................................22mA
Continuous Power Dissipation (TA = +85°C) (Note 1)
64-Pin TQFP-EP (derate 40.0mW/°C above +85°C) .........2.6W
Operating Temperature Range...............................0°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Note 1: Based on empirical data from the MAX3831/MAX3832 evaluation kit.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, LVDS differential load = 100±1%, CML load = 50±1% to VCC, all TTL inputs are open, TA = 0°C to
+85°C, unless otherwise noted. Typical values are at TA = +25°C and VCC = +3.3V.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Supply Current
ICC
CML inputs and outputs open, MAX3831
LVDS input VOS = 1.2V (Note 2) MAX3832
440 580
mA
480 614
LVDS INPUTS AND OUTPUTS
Input Voltage Range
Differential Input Threshold
VIN
VIDTH
0
-100
2400
+100
mV
mV
Threshold Hysteresis
Input Impedance
VHYST
RIN
90 mV
85 100 115
Input Common-Mode Current
IOS LVDS input, VOS = 1.2V
270 µA
Output Voltage High
VOH
1.475
V
Output Voltage Low
Differential Output Voltage
VOL
VOD
Figure 1
0.925
250
V
400 mV
Change in Magnitude of
Differential Output Voltage for
Complementary States
∆VOD
±25 mV
Output Offset Voltage
VOS
1.125
1.275
V
Change in Magnitude of Output
Offset Voltage for Complementary
States
∆VOS
±25 mV
Differential Output Impedance
Output Current
CML INPUTS AND OUTPUTS
Differential Output Voltage
Differential Output Impedance
Output Common-Mode Voltage
TRIEN = GND
TRIEN = VCC
Short outputs together (Note 3)
VODp-p
Single-Ended Input Voltage Range VIS
Differential Input Voltage Swing
Differential Input Impedance
Figure 2
>1 M
80 120
12 mA
640 800 1000
85 100 115
VCC - 0.2
VCC -
0.6
VCC +
0.4
400 1200
85 100 115
mVp-p
V
V
mVp-p
2 _______________________________________________________________________________________

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+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, LVDS differential load = 100±1%, CML load = 50±1% to VCC, all TTL inputs are open, TA = 0°C to
+85°C, unless otherwise noted. Typical values are at TA = +25°C and VCC = +3.3V.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
TTL INPUTS AND OUTPUTS
Input Voltage High
VIH
Input Voltage Low
VIL
Input Current High
IIH VIH = 2.0V
Input Current Low
IIL VIL = 0
Output Voltage High
VOH IOH = 20µA
Output Voltage Low
VOL IOL = 2mA
Output Impedance
TRIEN = GND
Note 2: When TEST = GND, the pattern generator will consume an additional 30mA.
Note 3: Guaranteed by design and characterization.
2.0 V
0.8 V
-250
-50 µA
-550
-100
µA
2.4 V
0.4 V
6 k
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, LVDS differential load = 100±1%, CML load = 50±1% to VCC, all TTL inputs are open, TA = 0°C to
+85°C, unless otherwise noted. Typical values are at TA = +25°C and VCC = +3.3V.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
4:1 MULTIPLEXER WITH CLOCK GENERATOR
Parallel Input Data Rate
622.08
Mbps
Maximum Parallel Input Skew
Serial-Data Output Rate
tes (Note 5)
±7.5
2.48832
ns
Gbps
Serial-Data Output Rise/Fall Time
Serial-Data Output Random Jitter
tr, tf 20% to 80%
SRJ (Note 6)
120 ps
3.5 psRMS
40 psp-p
Serial-Data Output Deterministic
Jitter
SDJ (Note 7)
8 18 psp-p
1:4 DEMULTIPLEXER
Serial-Data Input Rate
Serial-Data Setup Time
Serial-Data Hold Time
Parallel-Data Output Rate
Parallel-Clock Output Frequency
PCLKO to PDO_ Delay
LVDS Output Rise/Fall Time
LVDS Differential Skew
LVDS Channel-to-Channel Skew
LVDS Three-State Enable Time
tSU
tH
PDO±
PCLKO±
tCLK-Q
tSKEW1
tSKEW2
Figure 3
Figure 3
MAX3831
MAX3832
MAX3831, Figure 3
20% to 80%
Any differential pair
PDO1± to PDO4±
100
100
-100
2.48832
622.08
622.08
155.52
90
<100
30
300
350
65
Gbps
ps
ps
Mbps
MHz
ps
ps
ps
ps
ns
Note 4: AC characteristics are guaranteed by design and characterization.
Note 5: Relative to the positive edge of the 155MHz reference clock. PDI1 to PDI4 aligned to RCLKI at reset.
Note 6: Measured with a reference clock jitter of <1psRMS.
Note 7: Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse-width distortion.
_______________________________________________________________________________________ 3

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+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
PDO+
D
PDO-
VPDO-
SINGLE-ENDED OUTPUT
VPDO+
DIFFERENTIAL OUTPUT
0V (DIFF)
RL = 100
|VOD|
Figure 1. Definition of the LVDS Output
SDI+
SDI-
(SDI+) - (SDI-)
V VOD
VOH
VOS
VOL
+VOD
0V
-VOD
VODp-p = VPDO+ - VPDO-
200mV MIN
600mV MAX
VID
400mVp-p MIN
1200mVp-p MAX
Figure 2. Definition of the CML Input
SCLKI
SDI
tSCLK = 1 / fSCLK
tSU tH
PCLKO
PDO1–PDO4
tCLK-Q
NOTE: SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLKI = (SCLKI+) - (SCLKI-).
Figure 3. Timing Parameters
4 _______________________________________________________________________________________

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+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
SERIAL-DATA OUTPUT EYE DIAGRAM
223-1 PRBS PATTERN
SERIAL-DATA OUTPUT JITTER
SUPPLY CURRENT vs. TEMPERATURE
600
500 MAX3832
400 MAX3831
300
WIDEBAND RMS
JITTER = 2.48ps
200
100
50ps/div
10
8
6
4
2
0
-2
-4
-6
-8
-10
0
ELASTIC STORE RANGE
ERROR-FREE OPERATION
CHANNEL ALIGNED TO RCLKI
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
DATA TO RCLKI DELAY AT RESET (ns)
5ps/div
100
0
-50 -25
0
25 50 75 100
TEMPERATURE (°C)
SERIAL-DATA HOLD TIME
80
60
40
20
0
-20
-50 -25
0
25 50 75 100
TEMPERATURE (°C)
SERIAL-DATA SETUP TIME
100
MAX3831
PARALLEL CLOCK-TO-DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
300
80 250
200
60
150
40
100
20 50
0
-50 -25 0 25 50 75 100
TEMPERATURE (°C)
0
-50 -25
0
25 50 75 100
TEMPERATURE (°C)
_______________________________________________________________________________________ 5