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19-1467; Rev 2; 12/05
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
General Description
The MAX3880 deserializer with clock recovery is ideal
for converting 2.488Gbps serial data to 16-bit-wide,
155Mbps parallel data for SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts high-speed serial-data inputs and delivers low-
voltage differential-signal (LVDS) parallel clock and
data outputs for interfacing with digital circuitry.
The MAX3880 includes a low-power clock recovery and
data retiming function for 2.488Gbps applications. The
fully integrated phase-locked loop (PLL) recovers a
synchronous clock signal from the serial NRZ data
input; the signal is then retimed by the recovered clock.
The MAX3880’s jitter performance exceeds all
SDH/SONET specifications. An additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor and LVDS synchronization
inputs that enable data realignment and reframing.
The MAX3880 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP-EP (exposed
pad) package.
Applications
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross-Connects
Features
Single +3.3V Supply
910mW Operating Power
Fully Integrated Clock Recovery and Data
Retiming
Exceeds ANSI, ITU, and Bellcore Specifications
Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
2.488Gbps Serial to 155Mbps Parallel Conversion
LVDS Data Outputs and Synchronization Inputs
Tolerates >2000 Consecutive Identical Digits
Loss-of-Lock Indicator
Ordering Information
PART
TEMP. RANGE
MAX3880ECB
MAX3880ECB+
-40°C to +85°C
-40°C to +85°C
*Exposed pad
+Denotes lead-free package.
PIN-PACKAGE
64 TQFP-EP*
64 TQFP-EP*
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
0.01µF
+3.3V
VCC
FIL OUT+
IN+ MAX3866
PRE/POSTAMPLIFIER
OUT-
LOP
TTL
PHADJ+ PHADJ-
VCC
SDI+
SDI-
SLBI-
SLBI+
MAX3880
PD15+
PD15-
100*
PD0+
100*
PD0-
PCLK+
PCLK-
100*
SYNC+
SIS FIL+ FIL- GND
LOL SYNC-
SYSTEM
LOOPBACK
TTL
CF
1µF
TTL
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.
VCC
OVERHEAD
TERMINATION
________________________________________________________________ Maxim Integrated Products 1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.

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+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (VCC)...............................-0.5V to +7.0V
Input Voltage Level (SDI+, SDI-, SLBI+, SLBI-,
SYNC+, SYNC-)........................... (VCC - 0.5V) to (VCC + 0.5V)
Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................±10mA
Voltage at LOL, SIS, PHADJ+, PHADJ-,
FIL+, FIL- .................................................-0.5V to (VCC + 0.5V)
Output Current LVDS Outputs ............................................10mA
Continuous Power Dissipation (TA = +85°C)
TQFP (derate 33.3mW/°C above +85°C) .......................1.44W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential loads = 100±1%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VCC = +3.3V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Supply Current
ICC
SERIAL DATA INPUTS (SDI±, SLBI±)
275 380 mA
Differential Input Voltage
VID Figure 1
Single-Ended Input Voltage
VIS
Input Termination to Vcc
RIN
LVDS INPUTS AND OUTPUTS (SYNC±, PCLK±, PD_±)
50
VCC - 0.4
800 mVp-p
VCC + 0.2 V
50
Input Voltage Range
Differential Input Threshold
Threshold Hysteresis
Differential Input Resistance
Output High Voltage
Output Low Voltage
Differential Output Voltage
VI
VIDTH
VHYST
RIN
VOH
VOL
|VOD|
Differential input voltage = 100mV
Common-mode voltage = 50mV
Figure 2
0 2.4 V
-100
100 mV
78 mV
85 100 115
1.475
V
0.925
V
250 400 mV
Change in Magnitude of
Differential Output Voltage for
Complementary States
|VOD|
±25 mV
Output Offset Voltage
VOS
1.125
1.275
V
Change in Magnitude of Output
Offset Voltage for
Complementary States
VOS
±25 mV
Single-Ended Output
Resistance
RO
40 95 140
Change in Magnitude of Single-
Ended Output Resistance for
Complementary Outputs
RO
TTL INPUTS AND OUTPUTS (SIS, LOL)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
Output High Voltage
VOH
Output Low Voltage
VOL
±2.5 ±10
%
2.0 V
0.8 V
-10 +10 µA
2.4
VCC
V
0.4 V
2 _______________________________________________________________________________________

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+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential loads = 100±1%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VCC = +3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Serial Data Rate
SDI
2.488
Gbps
Parallel Output Data Rate
155.52
Mbps
Parallel Clock-to-Data Output
Delay
tCLK-Q Figure 5
200 450 900
ps
f = 70kHz (Note 2)
2.31 3.3
Jitter Tolerance
f = 100kHz
f = 1MHz
f = 10MHz
1.74 2.41
0.38 0.57
0.28 0.46
UIp-p
Tolerated Consecutive Identical
Digits
>2,000
Bits
Input Return Loss (SDI±, SLBI±)
100kHz to 2.5GHz
2.5GHz to 4.0GHz
-18
dB
-11
Note 1: AC characteristics are guaranteed by design and characterization.
Note 2: At jitter frequencies <70kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. The low-frequency
jitter tolerance outperforms the instrument’s measurement capability.
SDI+
25mV MIN
400mV MAX
SDI-
(SDI+) - (SDI-)
VID
50mVp-p MIN
800mVp-p MAX
Figure 1. Input Amplitude
PD+
D
VPD-
SINGLE-ENDED OUTPUT
VPD+
PD-
VPD+ - VPD-
DIFFERENTIAL OUTPUT
0V (DIFF)
RL = 100
|VOD|
V VOD
VOH
VOS
VOL
+VOD
0V
-VOD
VOD, p-p = VPD+ - VPD-
Figure 2. Driver Output Levels
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+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
RECOVERED DATA AND CLOCK
(DIFFERENTIAL OUTPUT)
MAX3880-01
DATA
223 - 1 PATTERN
CLOCK
1.64ns/div
SUPPLY CURRENT vs. TEMPERATURE
300
290
280 VCC = 3.6V
270
VCC = 3.0V
260
250
240
-50 -25
0
25 50 75 100
TEMPERATURE (°C)
10
1
0.1
10
JITTER TOLERANCE
100 1,000
JITTER FREQUENCY (kHz)
10,000
JITTER TOLERANCE vs. INPUT VOLTAGE
0.8
0.7 JITTER FREQUENCY = 1MHz
0.6
0.5
0.4 JITTER FREQUENCY
= 5MHz
0.3
0.2
0.1
0
10
SONET SPEC
100
INPUT VOLTAGE (mVp-p)
1,000
BIT ERROR RATE vs. INPUT VOLTAGE
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
INPUT VOLTAGE (mVp-p)
PARALLEL CLOCK TO DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
700
600
500
400
300
200
-50 -25 0 25 50
TEMPERATURE (°C)
75 100
4 _______________________________________________________________________________________

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+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Pin Description
PIN
1, 17, 25, 33,
41, 49, 56,
62, 64
2
3
4, 7, 10, 13,
24, 32, 40,
48, 57
5
NAME
GND
FIL+
FIL-
VCC
PHADJ+
6 PHADJ-
8 SDI+
9 SDI-
11 SLBI+
12 SLBI-
14 SIS
15 SYNC-
16
18
19
20, 22, 26,
28, 30, 34,
36, 38, 42,
44, 46, 50,
52, 54, 58, 60
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
63
SYNC+
PCLK-
PCLK+
PD0- to
PD15-
PD0+ to
PD15+
LOL
EP Exposed Pad
FUNCTION
Ground
Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
+3.3V Supply Voltage
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
Positive Serial Data Input. 2.488Gbps data stream.
Negative Serial Data Input. 2.488Gbps data stream.
Positive System Loopback Input. 2.488Gbps data stream.
Negative System Loopback Input. 2.488Gbps data stream.
Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
Negative Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
Positive Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
Negative Parallel Clock LVDS Output
Positive Parallel Clock LVDS Output
Negative Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
Positive Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kpull-up resistor). The
LOL monitor is valid only when a data stream is present on the inputs to the MAX3880.
Ground. This must be soldered to a circuit board for proper thermal performance (see Package
Information).
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