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eUMC
UM8326/8326B
Floppy Disk Data Separator (FDDS)"""" '.I,,',,:::,,,;,,,,.,,,::,,!,,,,,:,:, "",":' "'!,
Features
• Performs complete data separation function for floppy
disk drives
• Separates FM or MF M encoded data from any magnetic
media
• Eliminates several SSI and MSI devices normally used
for data separation
• No critical adjustments required
• Compatible with standard microsysterns' FDC 1791,
FDC 1793 and other floppy disk controllers
• Small 8-pin dual-in-line package
• +5 Volt only power supply
• TTL compatible inputs and outputs
General Description
The Floppy Disk Data Separator provides a low cost
solution to the problem of converting a single stream of
pulses from a floppy disk drive into separate clock and
data inputs for a Floppy Disk Controller.
The FDDS consists primarily of a clock divider, a long-term
timing corrector, a short-term timing corrector, and re-
clocking circuitry. Sypplied in an 8-pin Dual-in-Line
package to save board real estate, the FDDS operates on
+5 volts only and is TTL compatible on all inputs and
outputs.
The UM8326 is available in two versions; the UM8326,
which is intended for 514" disks and the UM8326B for
514" and 8" disks.
Pin Configuration
Block Diagram
vDD
SEPD
CDl
CDO
REFCLK
-CDO
--CDl
CLOCK
DIVIDER
- + 5V
- GND
-DSKD
EDGE
~ DATA/CLOCK '---
PULSE
~ SEPCLK
r - - -SEPARATION
REGENERATION
U ,. -LOGIC
LOGIC
SEPD
DETECTIOI\
LOGIC
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Absolute Maximum Ratings*
Operating Temperature Range . . . . . . . . . . OOC to + 70°C
Storage Temperature Range . . . . . . . . -55°C to + 150°C
Positive Voltage on any Pin, with respect to ground
................................. +8.0V
Negative Voltage on any Pin, with respect to ground
................................ -0.3V
Note:
When powering this device from laboratory or system
power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some
power supplies exhibit voltage spikes or "glitches" on their
UM8326/8326B
outputs when the AC power is switched on and off. In
addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists it is
suggested that a clamp circuit be used.
*Comments
Stresses above those listed may cause permanent damage
to the device. This is a stress rating only and functional
operation of the device at these or at any other condition
above those indicated in the operational sections of this
specification is not implied.
Electrical Characteristics
D.C. CHARACTERISTICS (TA = OoC to 70°C, Voo = +5V ± 5%, unless otherwise noted)
Parameter
Min. Typ.
Max.
Units
INPUT VOLTAGE LEVELS
Low Level V IL
High Level VIH
OUTPUT VOLTAGE LEVELS
Low Level VOL
High Level VOH
INPUT CURRENT
Leakage IlL
INPUT CAPACITANCE
All Inputs
POWER SUPPLY CURRENT
100
2.0
2.4
0.8 V
V
0.4 V
V
10 IlA
10 pF
60 mA
Conditions
IOL = 1.6 mA
IOH = -1001lA
O~VIN ~Voo
A.C. CHARACTERISTICS
Symbol
Parameter
fCY
fCY
tCKH
tCKL
tSOON
tSOOFF
tSPCK
tOLL
tOLH
REFCLK Frequency
REFCLK Frequency
REFCLK High Time
REFCLK Low Time
I
REFCLK to SEPD "ON" Delay
REFCLK to SEPD "OFF" Delay
REFCLK to SEPCLK Delay
DSKD Active Low Time
DSKD Active High Time
Min.
0.2
0.2
50
50
0.1
0.2
Typ.
100
100
Max.
4.3
8.3
2500
2500
100
100
100
Units
MHz
MHz
ns
ns
ns
ns
ns
Ils
Ils
Conditions
UM8326
UM8326B
6-30

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Pin Description
Pin No.
1
Name
Disk Data
2 Separated Clock
3 Reference Clock
4 Ground
5,6 Clock Divisor
7 Separated Data
8 Power Supply
UM8326/83268
Symbol
DSKD
SEPCLK
REFCLK
GND
COO
COl
SEPD
VDD
Function
Data input signal direct from disk drive. Contains combined
clock and data waveform.
Clock signal output from the FDDS derived from floppy disk
drive serial bit stream.
Reference clock input
Ground
COO and COl control the internal clock divider circuit. The
internal clock is a submultiple of the REFCLK according to
the following table:.
COl COO
00
01
10
1 -1
--
SEPD is the data output of the FDDS
Divisor
1
2
4
8
+5 volt power supply
Operational Description
A reference clock (REFCLK) of between 2 and 8 MHz is
divided by the FDDS to provide an internal clock. The
division ratio is selected by inputs ICDO and COl. The
reference clock and division ratio should be chosen per
table 1.
The FDDS detects the leading edges of the disk data
pulses and adjusts the phase of the internal clock to provide
the SEPARATED CLOCK output.
Separate short and long term timing correctors assure
accurate clock separation.
The internal clock frequency is nominally 16 times the
SEPCLK frequency. Depending on theinternal timing
correction, the internal clock may be a minimum of 12
times to a maximum of 22 times the SEPCLK frequency.
The reference clock (REFCLK) is divided to provide the
internal clock according to pins COO and COl.
Table 1. Clock Divider Selection Table
Drive
(8" or 5%")
Density
(DO or SO)
8 '00
8 SO
8 SO
5% DO
5% DO
5% SO
5% SO
5% SO
REFCLK
MHz
8
8
4
8
4
8
4
2
CD1
0
0
0
0
0
1
0
a
COO
Remarks
}0
1 Select either one
0
}1 Select either one
a
}0
1 Select anyone
a
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Timing Diagram (1)
INTCLK
SEPCLK.-J
U
:I
I4----.l
II
always two internal clock cycles
u
Timing Diagram (2)
UM8326/8326B
u
REFCLK
SEPCLK __________________________________________________________-'-~---
\='OLL ---r 1\.____________________DSKD__________________
'OLH
Typical System Configuration (5%" Drive, Double Density)
4 MHz CRYSTAL
DSCILLATOR
FLOPPY
DISK
DRIVE
DISK DATA
REFCLK
CDO CD1
GND GND
1 MHz
DERIVED CLOCK
6-32

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UM8326/83268
Comparison of Data Separator (UM9228·1, UM8329, UM8326)
PINOUT'COMPARISON
Function
Power Supply:
Vee
Vss
Precompensation:
EARLY
LATE
Amount Control
Read Data:
From FDD
To FDC
Data Row
Write Data:
From FDC
To FDD
Write Enable
Write Clock
179X!765MODE
Density
MASTER CLK to FDC
Extermal Clock I/P
TEST
179X/MODE ESP
DMA
VFO
VCO SYN
UM9228-1
Pin 3 Vee
13 Vss
9 EARLY
8 LATE
------
------
------
1 RD
5 SO
7 OW
10 WD
12 WDOUT
11 WEN
17 WCLK
------
------
------
18 FCLK
19 CLKIN
------
------
16 ORO
15 BACK
14 DROO/P
2 PROR
4 PFDV
6 VCOIN
20 VCOSNC
UM8329
Pin 20 Vee
10 Ground
13 EARLY
14 LATE
17 PO
18 P1
19 P2
1 DSKD
6 SPED
5 SEPCLK
12 WDIN
7 WDOUT
------
9 CLKOUT
2 FDCSEL
3 MINI
4 DENS
8 H LT /CLK
11 XTAL/CLKIN
16 TEST
15 HLD
------
------
------
------
------
------
------
UM8326
Pin 8 VDD
4 GND
------
------
------
------
------
1 DSKD
7 SPED
2 SEPCLK
------
------
------
------
5 COO
6 COl
------
------
3 REFCLK
------
------
------
------
------
------
------
------
------
Remarks
See B
Sec C
See 0
See E
See F
TIME PRECOMPENSATION
It is a more advanced function to solve "peak Shift"
problem. UM922S-1 defines compensation time to be
250ns according to IBM PC design. UMS329's compensa-
tion time is programmable, yet UMS326 does not have this
function.
WRITE DATA
UM922S-1 and UMS329 have write data function in IC, but
, UMS326 does not; and UM922S-1 has t.he "write enable"
pin to guarantee write function unfail.
MODE SE LECT .
UMS329 and UMS326 allow user to select different FDCs
and to interface different FDCs; but UM922S-1 is especial-
ly used in 5% FDD (MFM coding) interface.
DMA MODE
UM922S-1 can accept DMA request and d.efine the delay
time between two different DMA requests to be 5 /-lS to
guarantee system can work norm~lIy.
VFO CIRCUIT
Because UM922S-1 does not have VFO and PLL circuit,
user must combine MC4024 and MC4044 to build a
complete data separator. Please see UM922S-1 application
circuit intensively.
Ordering Information
Part Number
UMS326
UMS326B
Frequency Option
4MHz
SMHz
Package Type
Plastic
Plastic
6-33