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June 1988
DP8212 DP8212M 8-Bit Input Output Port
General Description
The DP8212 DP8212M is an 8-bit input output port con-
tained in a standard 24-pin dual-in-line package The device
which is fabricated using Schottky Bipolar technology is
part of National Semiconductor’s 8080A support family The
DP8212 DP8212M can be used to implement latches gat-
ed buffers or multiplexers Thus all of the major peripheral
and input output functions of a microcomputer system can
be implemented with this device
The DP8212 DP8212M includes an 8-bit latch with
TRI-STATE output buffers and device selection and con-
trol logic Also included is a service request flip-flop for the
generation and control of interrupts to the microprocessor
Features
Y 8-Bit data latch and buffer
Y Service request flip-flop for generation and control of
interrupts
Y 0 25 mA input load current
Y TRI-STATE TTL output drive capability
Y Outputs sink 15 mA
Y Asynchronous latch clear
Y 3 65V output for direct interface to INS8080A
Y Reduces system package count by replacing buffers
latches and multiplexers in microcomputer systems
8080A Microcomputer Family Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL F 6824
TL F 6824 – 1
RRD-B30M105 Printed in U S A

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Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b65 C to a160 C
All Output or Supply Voltages
b0 5V to a7V
All Input Voltages
b1 0V to 5 5V
Output Currents
125 mA
Maximum Power Dissipation at 25 C
Cavity Package
Molded Package
1903 mW
2005 mW
Derate cavity package 12 7 mW C above 25 C derate molded package
16 0 mW C above 25 C
Operating Conditions
Supply Voltage (VCC)
DP8212M
DP8212
Operating Temperaure (TA)
DP8212M
DP8212
Min
4 50
4 75
b55
0
Max
5 50
5 25
a125
a75
Units
VDC
VDC
C
C
Note Maximum ratings indicate limits beyond which perma-
nent damage may occur Continuous operation at these lim-
its is not intended and should be limited to those conditions
specified under DC electrical characteristics
Electrical Characteristics Min s TA s Max Min s VCC s Max unless otherwise noted
Symbol
Parameter
Conditions
Min Typ
IF Input Load Current
VF e 0 45V
STB DS2 CLR DI1 – DI8 Inputs
IF
Input Load Current MD Input
VF e 0 45V
IF
Input Load Current DS1 Input
VF e 0 45V
IR Input Leakage Current
VR e VCC Max
STB DS2 CLR DI1 – DI8 Inputs
IR
Input Leakage Current MD Input
VR e VCC Max
IR
Input Leakage Current DS1 Input
VR e VCC Max
VC
Input Forward Voltage Clamp
IC e b5 mA
VIL Input ‘‘Low’’ Voltage
DP8212M
DP8212
VIH Input ‘‘High’’ Voltage
20
VOL Output ‘‘Low’’ Voltage
IOL e 10 mA
DP8212M
IOL e 15 mA
DP8212
VOH Output ‘‘High’’ Voltage
IOH e 0 5 mA
DP8212M
3 40
40
IOH e 1 0 mA
DP8212
3 65 4 0
ISC Short-Circuit Output Current
VO e 0V VCC e 5V
l lIO
Output Leakage Current High
VO e 0 45V VCC Max
Impedance State
b15
ICC Power Supply Current
DP8212M
DP8212
90
90
Max
b0 25
b0 75
b1 0
10
30
40
b1
0 08
0 85
0 45
0 45
b75
20
145
130
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
mA
mA
mA
mA
Capacitance F e 1 MHz VBIAS e 2 5V VCC e 5V TA e 25 C
Symbol
Parameter
Min Typ Max Units
CIN DS1 MD Input Capacitance
CIN DS2 CLR STB DI1 – DI8 Input Capacitance
COUT
DO1–DO8 Output Capacitance
This parameter is sampled and not 100% tested
9 12 pF
5 9 pF
8 12 pF
2

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Switching Characteristics Min s TA s Max Min s VCC s Max
Symbol
Parameter
Conditions
DP8212M
Min Max
tPW Pulse Width
tPD Data to Output Delay
tWE Write Enable to Output Delay
tSET
Data Set-Up Time
tH Data Hold Time
tR Reset to Output Delay
tS Set to Output Delay
tE Output Enable Disable Time
tC Clear to Output Delay
Note 1 CL e 30 pF
Note 2 CL e 30 pF except for DP8212M
tE (DISABLE) CL e 5 pF
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 1)
40
30
50
20
30
55
35
50
65
Switching Conditions
1 Input Pulse Amplitude e 2 5V
2 Input Rise and Fall Times e 5 ns
3 Between 1V and 2V Measurements made at 1 5V with 15 mA
4 CL includes jig and probe capacitance
5 CL e 30 pF
6 CL e 30 pF except for DP8212M tE (DISABLE) CL e 5 pF
30 pF Test Load
DP8212
Min Max
30
30
40
15
20
40
30
45
55
Test Load
Alternate Test Load
(Refer to Timing Diagram)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
TL F 6824 – 2
TL F 6824 – 3
3

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Timing Diagram
TL F 6824 – 4
4

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Logic Diagram
TL F 6824 – 5
5