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CS4360
24-Bit, 192 kHz 6-channel D/A Converter
Features
24-bit Conversion
102 dB Dynamic Range
-91 dB THD+N
Low Clock Jitter Sensitivity
Digital Volume Control with Soft Ramp
– 119 dB Attenuation
– 1-dB Step Size
– Zero Crossing Click-Free Transitions
ATAPI Mixing
Logic Levels Between 5.0 V and 1.8 V
+3.3 V or +5 V Analog Power Supply
116 mW with 3.3 V Supply
Popguard Technology® for Control of Clicks
and Pops
Description
The CS4360 is a complete 6-channel digital-to-analog
system including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture, and a high tolerance to clock jitter.
The CS4360 accepts data at audio sample rates from
4 kHz to 200 kHz, consumes very little power, and oper-
ates over a wide power supply range. These features are
ideal for cost-sensitive, multi-channel audio systems in-
cluding DVD players, A/V receivers, set-top boxes,
digital TVs and VCRs, mini-component systems, and
mixing consoles.
ORDERING INFORMATION
CS4360-KZ -10 to 70 °C
28-pin TSSOP
CS4360-KZZ -10 to 70 °C Lead Free 28-pin TSSOP
CS4360-DZZ -40 to 85 °C Lead Free 28-pin TSSOP
CDB4360
Evaluation Board
I
RST
VLS
S C LK
LRCK
SD I N1
SD I N2
SD I N3
M CLK
÷2
DIF1/SCL/CCLK DIF0/SDA/CDIN M1/AD0/CS M2
VLC MUTEC1
MUTEC2 MUTEC3
C o ntr ol P o rt
I nt e r p o la ti o n F ilt e r
Int er polati on F ilter
I nt e r p o la ti o n F ilt e r
Int er polati on F ilter
I nt e r p o la ti o n F ilt e r
Int er polati on F ilter
Volum e Control
Mi xer
Volu me Control
Volum e Control
Mi xer
Volu m e Control
Volum e Control
Mi xer
Volu m e Control
E xternal
M ute C ontrol
∆Σ D A C
A n alo g Filter
∆Σ D A C
∆Σ D A C
A nalo g F ilte r
Analog Filter
∆Σ D A C
∆Σ D A C
A nalo g F ilte r
Analog Filter
∆Σ D A C
A nalo g F ilte r
VD GND GND VA
A O U T A1
A O UT B1
A O UT A2
A O UT B2
A O U T A3
A O UT B3
VQ
FILT+
http://www.cirrus.com
©Copyright Cirrus Logic, Inc. 2004
(All Rights Reserved)
JUL ‘04
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CS4360
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................... 5
2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 7
3. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 8
SPECIFIED OPERATING CONDITIONS ................................................................................. 8
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8
ANALOG CHARACTERISTICS (CS4360-KZ/KZZ) .................................................................. 9
ANALOG CHARACTERISTICS (CS4360-DZZ) ..................................................................... 11
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE......................... 13
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE........................................... 16
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE ....................................... 17
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE ....................................... 18
DC ELECTRICAL CHARACTERISTICS................................................................................. 19
DIGITAL INPUT CHARACTERISTICS ................................................................................... 19
DIGITAL INTERFACE SPECIFICATIONS.............................................................................. 20
THERMAL CHARACTERISTICS AND SPECIFICATIONS .................................................... 20
4. APPLICATIONS ...................................................................................................................... 21
4.1 Sample Rate Range/Operational Mode Select ................................................................ 21
4.1.1 Stand-alone Mode ............................................................................................... 21
4.1.2 Control Port Mode ............................................................................................... 21
4.2 System Clocking .............................................................................................................. 21
4.3 Digital Interface Format .................................................................................................... 22
4.3.1 Stand-alone Mode ............................................................................................... 22
4.3.2 Control Port Mode .............................................................................................. 23
4.4 De-emphasis Control ....................................................................................................... 23
4.4.1 Stand-alone Mode ............................................................................................... 24
4.4.2 Control Port Mode ............................................................................................... 24
4.5 Recommended Power-up Sequence ............................................................................... 24
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com/
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is sub-
ject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of
relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and con-
ditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsi-
bility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement
of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied
under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the
information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated
circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes,
or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANT-
ED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS
OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE
SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOM-
ER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF
THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER
AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor. Purchase of I²C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies con-
veys a license under the Philips I²C Patent Rights to use those components in a standard I²C system.
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CS4360
4.5.1 Stand-alone Mode ............................................................................................... 24
4.5.2 Control Port Mode ............................................................................................... 24
4.6 Popguard® Transient Control .......................................................................................... 24
4.6.1 Power-up ............................................................................................................. 24
4.6.2 Power-down ........................................................................................................ 24
4.6.3 Discharge Time ................................................................................................... 25
4.7 Mute Control .................................................................................................................... 25
4.8 Grounding and Power Supply Arrangements .................................................................. 25
4.8.1 Capacitor Placement ........................................................................................... 25
4.8.2 Power Supply Sections ....................................................................................... 25
4.9 Control Port Interface ...................................................................................................... 25
4.9.1 Memory Address Pointer (MAP) ......................................................................... 26
4.9.1a INCR (Auto Map Increment) ................................................................ 26
4.9.1b MAP0-3 (Memory Address Pointer) ..................................................... 26
4.9.2 I²C Mode ............................................................................................................. 26
4.9.2a I²C Write ............................................................................................... 26
4.9.2b I²C Read ............................................................................................... 27
4.9.3 SPI Mode ............................................................................................................ 27
4.9.3a SPI Write .............................................................................................. 28
5. REGISTER QUICK REFERENCE ......................................................................................... 29
6. REGISTER DESCRIPTIONS .................................................................................................. 30
6.1 Mode Control 1 (address 01h) ......................................................................................... 30
6.1.1 Auto-mute (AMUTE) Bit 7 ....................................................................................... 30
6.1.2 Digital Interface Format (DIF) Bit 4-6 ...................................................................... 30
6.1.3 De-emphasis Control (DEM) Bit 2-3........................................................................ 31
6.1.4 Functional Mode (FM) Bit 0-1.................................................................................. 31
6.2 Invert Signal (address 02h) ............................................................................................. 31
6.2.1 Invert Signal Polarity (INV_xx) Bit 0-5 ..................................................................... 31
6.3 Mixing Control Pair 1 (Channels A1 & B1) (address 03h)
Mixing Control Pair 2 (Channels A2 & B2) (address 04h)
Mixing Control Pair 3 (Channels A3 & B3) (address 05h)............................................. 31
6.3.1 ATAPI Channel Mixing and Muting (atapi) Bit 0-3................................................... 32
6.4 Volume Control (addresses 06h - 0Bh) ........................................................................... 33
6.4.1 MUTE (MUTE) Bit 7 ................................................................................................ 33
6.4.2 VOLUME CONTROL (xx_VOL) Bit 0-6 ................................................................... 33
6.5 Mode Control 2 (address 0Dh) ......................................................................................... 33
6.5.1 Soft Ramp and Zero Cross CONTROL (SZC) Bit 6-7 ............................................. 33
6.5.2 Control Port Enable (CPEN) Bit 5 ........................................................................... 34
6.5.3 Power Down (PDN) Bit 4......................................................................................... 34
6.5.4 Popguard® Transient Control (POPG) Bit 3 ........................................................... 34
6.5.5 Freeze Controls (FREEZE) Bit 2............................................................................. 35
6.5.6 Master Clock DIVIDE ENABLE (MCLKDIV) Bit 1 ................................................... 35
6.5.7 Single Volume Control (SNGLVOL) Bit 0 ................................................................ 35
6.6 Revision Register (Read Only) (address 0Dh) ................................................................ 35
6.6.1 Revision Indicator (REV) [Read Only] Bit 0-3 ......................................................... 35
7. PARAMETER DEFINITIONS .................................................................................................. 36
Total Harmonic Distortion + Noise (THD+N) .......................................................................... 36
Dynamic Range ...................................................................................................................... 36
Interchannel Isolation ............................................................................................................. 36
Interchannel Gain Mismatch ................................................................................................... 36
Gain Error ............................................................................................................................... 36
Gain Drift ................................................................................................................................ 36
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CS4360
8. REFERENCES ........................................................................................................................ 36
9. PACKAGE DIMENSIONS ....................................................................................................... 37
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Typical Connection Diagram .......................................................................................... 7
Output Test Load ......................................................................................................... 10
Maximum Loading ........................................................................................................ 10
Single-speed Stopband Rejection ................................................................................ 14
Single-speed Transition Band ...................................................................................... 14
Single-speed Transition Band (Detail) ......................................................................... 14
Single-speed Passband Ripple .................................................................................... 14
Double-speed Stopband Rejection .............................................................................. 14
Double-speed Transition Band ..................................................................................... 14
Double-speed Transition Band (Detail) ........................................................................ 15
Double-speed Passband Ripple ................................................................................... 15
Serial Mode Input Timing ............................................................................................. 16
Control Port Timing - I²C Mode .................................................................................... 17
Control Port Timing - SPI Mode ................................................................................... 18
Left Justified up to 24-Bit Data ..................................................................................... 23
I2S, up to 24-Bit Data ................................................................................................... 23
Right Justified Data ...................................................................................................... 23
De-emphasis Curve ..................................................................................................... 23
I²C Write ....................................................................................................................... 27
I²C Read ....................................................................................................................... 27
SPI Write ...................................................................................................................... 28
ATAPI Block Diagram .................................................................................................. 32
LIST OF TABLES
Table 1. CS4360 Stand-alone Operational Mode............................................................................. 21
Table 2. CS4360 Control Port Operational Mode ............................................................................. 21
Table 3. Single-speed Mode Standard Frequencies ........................................................................ 21
Table 4. Double-speed Mode Standard Frequencies ....................................................................... 21
Table 5. Quad-speed Mode Standard Frequencies ......................................................................... 22
Table 6. Digital Interface Format - Stand-alone Mode...................................................................... 22
Table 7. Power Supply Control Sections .......................................................................................... 25
Table 8. Digital Interface Formats - Control Port Mode .................................................................... 30
Table 9. ATAPI Decode .................................................................................................................... 32
Table 10. Example Digital Volume Settings ..................................................................................... 33
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1. PIN DESCRIPTION
VLS
SDIN1
SDIN2
SDIN3
SCLK
LRCK
MCLK
VD
GND
RST
DIF1/SCL/CCLK
DIF0/SDA/CDIN
M1/AD0/CS
VLC
1 28
2 27
3 26
4 25
5 24
6 23
7 CS4360 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
CS4360
MUTEC1
AOUTA1
AOUTB1
MUTEC2
AOUTA2
AOUTB2
VA
GND
AOUTA3
AOUTB3
MUTEC3
VQ
FILT+
M2
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