16Mx16, 7.5 - 15ns, P12, M-Densus
256 Megabit Synchronous DRAM
High Density Memory Device
The M-Densus series is a family of interchangeable memory modules. The 256 Megabit SDRAM is a member of
this family which utilizes the new and innovative space saving TSOP stacking technology. The modules are
constructed with 8 Meg x 16 SDRAMs.
This 128 Megabit based M-Densus module, the
DPSD16MX16TY5 has been designed to fit in the same
footprint as the 8 Meg x 16 SDRAM TSOP monolithic and
128 Megabit SDRAM based family of M-Densus modules.
This allows the memory board designer to upgrade the
memory in their products without redesigning the
memory board, thus saving time and money.
• Configuration Available:
16 Meg x 16 bit (with two Chip Selects)
• Clock F6re6q[1u],e8n3c[y1:], 100, 125, 133 MHz (max.)
• PC100 and PC133 Compatible
• 3.3V Supply
• LVTTL Compatible I/O
• Four Bank Operation
• Programmable Burst Type, Burst Length,
and CAS Latency
• 4096 Cycles / 64 ms
• Auto and Self Refresh
• Package: TSOP Leadless Stack
NOTES:  Available in Industrial Temperature Ranges Only.
 Available in Commercial Temperature Range Only.
FUNCTIONAL BLOCK DIAGRAM
A0 - A11
DQ0 - DQ15
Row Address: A0 - A11
Column Address: A0 - A8
Bank Select Address
Data In / Data Out
Column Address Strobes
Row Address Enables
Data Write Enable
Upper & Lower
Data Input/Output Mask
Data Output Power/Ground
Reserved for Future Use
This document contains information on a product under consideration for
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right
to change or discontinue information on this product without prior notice.