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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Designer's Data Sheet
TMOS E-FET.
Power Field Effect Transistor
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also offers a drain–to–source diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls,
and other inductive loads. The avalanche energy capability is
specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
Avalanche Energy Specified
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
MTY100N10E
Motorola Preferred Device
TMOS POWER FET
100 AMPERES
100 VOLTS
RDS(on) = 0.011 OHM
®
D
G
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1 M)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp 10 ms)
Drain Current — Continuous @ TC = 25°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 100 Apk, L = 0.1 mH, RG = 25 )
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
CASE 340G–02, STYLE 1
TO–264
S
Symbol
VDSS
VDGR
VGS
VGSM
ID
IDM
PD
TJ, Tstg
EAS
Value
100
100
± 20
± 40
100
300
300
2.38
– 55 to 150
250
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
°C
mJ
RθJC
RθJA
TL
0.42 °C/W
40
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
© MMoototroorlao,lIancT. 1M99O5S Power MOSFET Transistor Device Data
1

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MTY100N10E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0, ID = 250 µA)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V(BR)DSS
100
115
— Vdc
— mV/°C
IDSS
µAdc
— — 10
— — 200
IGSS
— — 100 nAdc
VGS(th)
2.0 —
—7
4 Vdc
— mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 50 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 100 Adc)
(ID = 50 Adc, TJ = 125°C)
Forward Transconductance (VDS = 6 Vdc, ID = 50 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(VDD = 50 Vdc, ID = 100 Adc,
VGS = 10 Vdc,
RG = 9.1 )
(VDS = 80 Vdc, ID = 100 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 100 Adc, VGS = 0 Vdc)
(IS = 100 Adc, VGS = 0 Vdc, TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
0.011
Ohm
Vdc
— 1.0 1.2
— — 1.0
30 49 — mhos
7600 10640
pF
3300
4620
1200
2400
— 48 96 ns
— 490 980
— 186 372
— 384 768
— 270 378 nC
— 50 —
— 150 —
— 118 —
Vdc
— 1 1.2
— 0.9 —
Reverse Recovery Time
(See Figure 14)
(IS = 100 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
trr
ta
tb
QRR
LD
— 145 —
— 90 —
— 55 —
— 2.34 —
— 4.5 —
ns
µC
nH
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
LS
— 13 — nH
2 Motorola TMOS Power MOSFET Transistor Device Data

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TYPICAL ELECTRICAL CHARACTERISTICS
MTY100N10E
200
VGS = 10 V
9V
160
120
80
8V
TJ = 25°C
7V
6V
120
100 VDS 10 V
80
60
40
40
5V
0
0 2 4 6 8 10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
20
100°C
TJ = – 55°C
25°C
0
2 3 4 5 6 7 8 9 10
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0.018
0.016
0.014
VGS = 10 V
TJ = 100°C
0.012
0.01
25°C
0.008
– 55°C
0.006
0
50 100 150
ID, DRAIN CURRENT (AMPS)
200
Figure 3. On–Resistance versus Drain Current
and Temperature
0.011
0.0105
TJ = 25°C
VGS = 10 V
0.01
0.0095
0.009
15 V
0.0085
0.008
0
50 100 150
ID, DRAIN CURRENT (AMPS)
200
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1.8
VGS = 10 V
1.6 ID = 50 A
1.4
1.2
1
0.8
1000000
100000
VGS = 0 V
1000
100
10
TJ = 125°C
100°C
25°C
0.6
– 50
– 25 0
25 50
75 100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
150
1
0 20 40 60 80 100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
120
Motorola TMOS Power MOSFET Transistor Device Data
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MTY100N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
24000
20000
16000
VDS = 0 V
Ciss
VGS = 0 V
TJ = 25°C
12000 Crss
8000
Ciss
Coss
4000
Crss
0
10 5
0
5
VGS VDS
10 15 20
25
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4 Motorola TMOS Power MOSFET Transistor Device Data

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12
10
8
Q1
6
120
QT
100
VGS
80
Q2
60
4 TJ = 25°C 40
ID = 100 A
2 20
Q3
0
VDS
0
0 50 100 150 200 250 300
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate Charge versus Gate–to–Source Voltage
10000
1000
100
VDD = 50 V
ID = 100 A
VGS = 10 V
TJ = 25°C
tr
tf
td(off)
MTY100N10E
td(on)
10
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
100
80
VGS = 0 V
TJ = 25°C
60
40
20
0
0.5 0.6 0.7 0.8 0.9
1
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
1.1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5