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August 1996
COP912C COP912CH 8-Bit Microcontroller
General Description
The COP912C COP912CH are members of the COP8TM
8-bit MicroController family They are fully static Microcon-
trollers fabricated using double-metal silicon gate micro-
CMOS technology These low cost MicroControllers are
complete microcomputers containing all system timing in-
terrupt logic ROM RAM and I O necessary to implement
dedicated control functions in a variety of applications Fea-
tures include an 8-bit memory mapped architecture
MICROWlRETM serial I O a 16-bit timer counter with cap-
ture register and a multi-sourced interrupt Each I O pin has
software selectable options to adapt the device to the spe-
cific application The device operates over voltage ranges
from 2 3V to 4 0V (COP912C) and from 4 0V to 5 5V
(COP912CH) High throughput is achieved with an efficient
regular instruction set operating at a minimum of 2 ms per
instruction rate
Key Features
Y Lowest cost COP8 microcontroller
Y 16-bit multi-function timer supporting
PWM mode
External event counter mode
Input capture mode
Y 768 bytes of ROM
Y 64 bytes of RAM
I O Features
Y Memory mapped I O
Y Software selectable I O options (TRI-STATE Output
Push-Pull Output Weak Pull-Up Input High Impedance
Input)
Y Schmitt trigger inputs on Port G
Y MICROWIRE PLUSTM Serial I O
Y Packages 20 DIP SO with 16 I O pins
CPU Instruction Set Features
Y Instruction cycle time of 2 ms for COP912CH and
2 5 ms for COP912C
Y Three multi-sourced interrupts servicing
External Interrupt with selectable edge
Timer interrupt
Software interrupt
Y Versatile and easy to use instruction set
Y 8-bit Stack Pointer (SP) stack in RAM
Y Two 8-bit Register Indirect Memory Pointers (B X)
Fully Static CMOS
Y Low current drain (typically k 1 mA)
Y Single supply operation 2 3V to 4 0V or 4 0V to 5 5V
Y Temperature range 0 C to a70 C
Development Support
Y Emulation and OTP devices
Y Real time emulation and full program debug offered by
MetaLink Development System
Applications
Y Electronic keys and switches
Y Remote Control
Y Timers
Y Alarms
Y Small industrial control units
Y Low cost slave controllers
Y Temperature meters
Y Small domestic appliances
Y Toys and games
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
COP8TM MICROWIRE PLUSTM WATCHDOGTM and MICROWIRETM are trademarks of National Semiconductor Corporation
PC is a registered trademark of International Business Machines Corp
iceMasterTM is a trademark of MetaLink Corporation
C1996 National Semiconductor Corporation TL DD12060
RRD-B30M96 Printed in U S A
TL DD 12060 – 1
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Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (VCC)
Voltage at Any Pin
6 0V
b0 3V to VCC a0 3V
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
80 mA
80 mA
Storage Temperature Range
b65 C to a150 C
Note Absolute maximum ratings indicate limits beyond which damage
to the device may occur DC and AC electrical specifications are not
ensured when operating the device at absolute maximum ratings
DC Electrical Characteristics COP912C COP912CH 0 C s TA s a70 C unless other specified
Parameter
Conditions
Min Typ Max
Operating Voltage
912C
912CH
Power Supply Ripple 1 (Note 1)
Supply Current (Note 2)
CKI e 4 MHz
CKI e 4 MHz
HALT Current
INPUT LEVELS (VIH VIL)
Reset CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage TRI-STATE Leakage
Input Pullup Current
G-Port Hysteresis
Output Current Levels
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
Allowable Sink Source Current Per Pin
Peak to Peak
VCC e 5 5V tc e 2 5 ms
VCC e 4 0V tc e 2 5 ms
VCC e 5 5V CKI e 0 MHz
VCC e 5 5V
VCC e 5 5V
VCC e 4 0V VOH e 3 8V
VCC e 2 3V VOH e 1 8V
VCC e 4 0V VOL e 1 0V
VCC e 2 3V VOL e 0 4V
23
40
0 9 VCC
0 7 VCC
b2
04
02
40
07
k1
0 05 VCC
40
55
0 1 VCC
60
25
8
0 1 VCC
0 2 VCC
a2
250
0 35 VCC
3
Input Capacitance (Note 3)
7
Load Capacitance on D2 (Note 3)
1000
Note 1 Rate of voltage change must be less then 0 5 V ms
Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open
Note 3 Characterized not tested
Units
V
V
V
mA
mA
mA
V
V
V
V
mA
mA
V
mA
mA
mA
mA
mA
pF
pF
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TL DD 12060 – 2
FIGURE 1 MICROWIRE PLUS Timing
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Typical Performance Characteristics
Halt IDD
Dynamic IDD (Crystal Clock Option)
TL DD 12060 – 16
Port L G Weak Pull-Up
Source Current
TL DD 12060 – 17
Port L G Push-Pull Source Current
TL DD 12060 – 18
Port L G Push-Pull Sink Current
TL DD 12060 – 19
Port D Source Current
TL DD 12060 – 20
Port D Sink Current
TL DD 12060 – 21
TL DD 12060 – 22
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AC Electrical Characteristics COP912C COP912CH 0 C s TA s a70 C unless otherwise specified
Parameter
Conditions
Min Typ Max Units
INSTRUCTION CYCLE TIME (tc)
Crystal Resonator
R C Oscillator
Inputs
tSetup
tHold
Output Propagation Delay
tPD1 tPD0
SO SK
All Others
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
4 0V s VCC s 5 5V
2 3V s VCC k 4 0V
4 0V s VCC s 5 5V
2 3V s VCC k 4 0V
4 0V s VCC s 5 5V
2 3V s VCC k 4 0V
4 0V s VCC s 5 5V
2 3V s VCC k 4 0V
RL e 2 2 kX CL e 100 pF
4 0V s VCC s 5 5V
2 3V s VCC k 4 0V
4 0V s VCC s 5 5V
2 3V s VCC k 4 0V
2
25
3
75
200
500
60
150
1 tc
1 tc
1 tc
1 tc
DC
DC
DC
DC
07
1 75
1
5
ms
ms
ms
ms
ns
ns
ns
ns
ms
ms
ms
ms
MICROWIRE Setup Time (tmWS)
MICROWIRE Hold Time (tmWH)
MICROWIRE Output
Propagation Delay (tmPD)
Reset Pulse Width
20 ns
56 ns
220 ns
1 0 ms
COP912C COP912CH Pinout
20 DIP
Top View
20 SO Wide
TL DD 12060–3
Order Number COP912C-XXX N COP912CH-XXX N
TL DD 12060 – 4
Order Number COP912C-XXX WM
COP912CH-XXX WM
FIGURE 2 COP912C COP912CH Pinout
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Pin Description
VCC and GND are the power supply pins
CKI is the clock input This can come from an external
source a R C generated oscillator or a crystal (in conjunc-
tion with CKO) See Oscillator description
RESET is the master reset input See Reset description
PORT L is an 8-bit I O port
There are two registers associated to configure the L port a
data register and a configuration register Therefore each L
I O bit can be individually configured under software control
as shown below
Port L Config
0
0
1
1
Port L Data
0
1
0
1
PORT L
Setup
Hi-Z Input (TRI-STATE)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Three data memory address locations are allocated for this
port one each for data register 00D0 configuration regis-
ter 00D1 and the input pins 00D2
PORT G is an 8-bit port with 6 I O pins (G0–G5) and 2 input
pins (G6 G7)
All eight G-pins have Schmitt Triggers on the inputs
There are two registers associated to configure the G port
a data register and a configuration register Therefore each
G port bit can be individually configured under software con-
trol as shown below
Port G
Config
0
0
1
1
Port G
Data
0
1
0
1
PORT G
Setup
Hi-Z Input (TRI-STATE)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Three data memory address locations are allocated for this
port one for data register 00D4 one for configuration reg-
ister 00D5 and one for the input pins 00D6 Since G6
and G7 are Hi-Z input only pins any attempt by the user to
configure them as outputs by writing a one to the configura-
tion register will be disregarded Reading the G6 and G7
configuration bits will return zeroes Note that the chip will
be placed in the Halt mode by writing a ‘‘1’’ to the G7 data
bit
Six pins of Port G have alternate features
G0 INTR (an external interrupt)
G3 TIO (timer counter input output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I O)
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input general purpose input (if clock op-
tion is R C- or external clock)
Pins G1 and G2 currently do not have any alternate func-
tions
The selection of alternate Port G functions are done through
registers PSW 00EF to enable external interrupt and
CNTRL 00EE to select TIO and MICROWIRE operations
Functional Description
The internal architecture is shown in the block diagram
Data paths are illustrated in simplified form to depict how
the various logic elements communicate with each other in
implementing the instruction set of the device
ALU AND CPU REGISTERS
The ALU can do an 8-bit addition subtraction logical or
shift operations in one cycle time There are five CPU regis-
ters
A is the 8-bit Accumulator register
PC is the 15-bit Program Counter register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is the 8-bit address register and can be auto incre-
mented or decremented
X is the 8-bit alternate address register and can be auto
incremented or decremented
SP is the 8-bit stack pointer which points to the subroutine
stack (in RAM)
B X and SP registers are mapped into the on chip RAM
The B and X registers are used to address the on chip RAM
The SP register is used to address the stack in RAM during
subroutine calls and returns The SP must be preset by soft-
ware upon initialization
MEMORY
The memory is separated into two memory spaces program
and data
PROGRAM MEMORY
Program memory consists of 768 x 8 ROM These bytes of
ROM may be instructions or constant data The memory is
addressed by the 15-bit program counter (PC) There are no
‘‘pages’’ of ROM the PC counts all 15 bits ROM can be
indirectly read by the LAlD instruction for table lookup
DATA MEMORY
The data memory address space includes on chip RAM I O
and registers Data memory is addressed directly by the in-
struction or indirectly through B X and SP registers The
device has 64 bytes of RAM Sixteen bytes of RAM are
mapped as ‘‘registers’’ these can be loaded immediately
decremented and tested Three specific registers X B and
SP are mapped into this space the other registers are avail-
able for general usage
Any bit of data memory can be directly set reset or tested
I O and registers (except A and PC) are memory mapped
therefore I O bits and register bits can be directly and indi-
vidually set reset and tested
RESET
The RESET input pin when pulled low initializes the micro-
controller Upon initialization the ports L and G are placed
in the TRl-STATE mode The PC PSW and CNTRL regis-
ters are cleared The data and configuration registers for
ports L and G are cleared The external RC network shown
in Figure 3 should be used to ensure that the RESET pin is
held low until the power supply to the chip stabilizes
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