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DDR SDRAM 256Mb F-die (x8, x16)
DDR SDRAM
256Mb F-die DDR400 SDRAM Specification
Revision 1.1
Rev. 1.1 August. 2003

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DDR SDRAM 256Mb F-die (x8, x16)
256Mb F-die Revision History
Revison 1.0 (June. 2003)
1. First release
Revison 1.1 (August. 2003)
1. Added x8 org (K4H560838F)
DDR SDRAM
Rev. 1.1 August. 2003

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DDR SDRAM 256Mb F-die (x8, x16)
DDR SDRAM
Key Features
• 200MHz Clock, 400Mbps data rate.
• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
Ordering Information
Part No.
K4H560838F-TCCC
K4H560838F-TCC4
K4H561638F-TCCC
K4H561638F-TCC4
Org.
32M x 8
16M x 16
Max Freq.
CC(DDR400@CL=3)
C4(DDR400@CL=3)
CC(DDR400@CL=3)
C4(DDR400@CL=3)
Interface
SSTL2
SSTL2
Package
66pin TSOP II
66pin TSOP II
Operating Frequencies
Speed @CL3
CL-tRCD-tRP
- CC(DDR400@CL=3)
200MHz
3-3-3
*CL : CAS Latency
- C4(DDR400@CL=3)
200MHz
3-4-4
Rev. 1.1 August. 2003

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DDR SDRAM 256Mb F-die (x8, x16)
Pin Description
16Mb x 16
32Mb x 8
DDR SDRAM
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 66Pin TSOPII 57
11 (400mil x 875mil) 56
12 (0.65mm Pin Pitch) 55
13 54
14 Bank Address
15 BA0~BA1
16
53
52
51
17 50
18
Auto Precharge
A10
49
19 48
20 47
21 46
22 45
23 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
256Mb Package Pinout
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Organization
32Mx8
16Mx16
Row Address
A0~A12
A0~A12
Column Address
A0-A9
A0-A8
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.1 August. 2003

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DDR SDRAM 256Mb F-die (x8, x16)
Package Physical Demension
#66 #34
DDR SDRAM
Units : Millimeters
#1
(1.50)
(R0.15)
(0.71)
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASSY OUT QUALITY
(10×)
(10×)
#33
0.125
+0.075
-0.035
22.22±0.10
0.65TYP
0.65±0.08
(10×)
0.30±0.08
(10×)
0.10 MAX
[ 0.075 MAX ]
0.25TYP
0×~8×
66pin TSOPII / Package dimension
Rev. 1.1 August. 2003