2.1.1 ARM1136JF-S Platform Modules
The modules that are used in the ARM1136JF-S Platform include the following:
• The ARM1136JF-S CPU core—Based on the ARM® v6 architecture. It supports the
ARM Thumb® instruction set, Jazelle® technology to enable direct execution of Java™ byte codes,
and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.
• The VFP11 coprocessor—An ARM enhanced IEEE® 754 numeric coprocessor that can be used
to support and enhance 3D graphics, gaming, high resolution audio, Java, and other
• A Multi-Level Cache system—Consisting of a powerful L2 Cache Controller, 128 Kbytes unified
L2 cache memory and L2 cache monitor. The L2 cache controller (L2CC) module has been
optimized by ARM to Freescale’s specifications. The L1 cache provides 16 Kbytes for instruction
and 16 Kbytes for data.
• Multi-Layer 6 × 5 AHB Smart Speed Crossbar Switch (MAX)—The L2CC master ports, the
off-platform alternate bus masters, and the ARM11 processor’s peripheral AHB arbitrate for
memory and peripherals via a 6 × 5 Multi-Layer AHB crossbar switch. The design of the MAX
allows concurrent transactions to proceed from any slave port to any master port. That is, it is
possible for five MAX slave ports to be active at the same time as a result of five independent
If a particular slave port is simultaneously requested by more than one master port, arbitration logic
exists in the MAX to allow the higher priority master port to be granted access to the slave, while
stalling the other requestor(s) until that transaction is complete. The slave port arbitration schemes
supported are fixed, programmable fixed, round-robin, and programmable default parking.
• L2 Memory System—The embedded 16 Kbytes SRAM and 32 Kbytes ROM are accessible by the
ARM CPU and the Enhanced DMA (eDMA) controller. ROM holds the High Assurance Boot
2.2 Smart Power Management by Design
The i.MX31 and i.MX31L processors’ power management system includes an effective combination of
established and ground-breaking (patent pending) technologies to ensure the following design goals are
• The operation of the IC is well balanced, providing the optimum trade-off between performance
and power consumption.
• Power is expended only when it is actually required by an application.
• When power is required, the minimum amount of power is used to complete the application.
There is always a trade-off between the potential performance that can be achieved and the leakage current
that is unavoidable to obtain a high level of performance because higher performance requires solid state
devices with increased leakage. To ensure the best possible performance trade-off, the i.MX31 and
i.MX31L processors are manufactured using a 90-nm, low-power process to ensure minimum power
dissipation by leakage. At the same time, dual Vt technology is used to incorporate the high performance
transistors in places where the performance is critical, therefore, producing the best overall trade-off
between performance and leakage.
i.MX31 and i.MX31L Multimedia Applications Processors Product Brief, Rev. 0.6
4 Freescale Semiconductor