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®
Data Sheet
X5328, X5329
(Replaces X25328, X25329)
October 17, 2005
FN8132.1
CPU Supervisor with 32Kbit SPI EEPROM
FEATURES
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence
—Reset signal valid to VCC = 1V
• Long battery life with low power consumption
—<1µA max standby current
—<400µA max active current during read
• 32Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lockprotection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
WP
SI
SO
SCK
CS
Data
Register
Command
Decode &
Control
Logic
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Supply Voltage Supervision, and Block
Lock Protect Serial EEPROM Memory in one package.
This combination lowers system cost, reduces board
space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions by holding
RESET/RESET active when VCC falls below a mini-
mum VCC trip point. RESET/RESET remains asserted
until VCC returns to proper operating level and stabi-
lizes. Five industry standard VTRIP thresholds are
available, however, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold in applica-
tions requiring higher precision.
Protect Logic
Status
Register
8Kbits
8Kbits
16Kbits
VCC
VTRIP
+
-
Reset
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
X5328 = RESET
X5329 = RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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X5328, X5329
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
X5328P-4.5A
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
X5329P-4.5A
PART
MARKING
VCC RANGE
TEMP
(V) VTRIP RANGE RANGE (°C)
PACKAGE
4.5-5.5
4.5-4.75
0 to 70 8 Ld PDIP
X5328PZ-4.5A (Note) X5328P Z AL X5329PZ-4.5A (Note) X5329P Z AL
0 to 70 8 Ld PDIP (Pb-free)
X5328PI-4.5A
X5329PI-4.5A
-40 to 85 8 Ld PDIP
X5328PIZ-4.5A (Note) X5328P Z AM X5329PIZ-4.5A (Note) X5329P Z AM
-40 to 85 8 Ld PDIP (Pb-free)
X5328S8-4.5A
X5328 AL X5329S8-4.5A
0 to 70 8 Ld SOIC
X5328S8Z-4.5A (Note) X5328 Z AL X5329S8Z-4.5A (Note) X5329 Z AL
0 to 70 8 Ld SOIC (Pb-free)
X5328S8I-4.5A
X5328 AM X5329S8I-4.5A
-40 to 85 8 Ld SOIC
X5328S8IZ-4.5A
(Note)
X5328 Z AM X5329S8IZ-4.5A
(Note)
X5329 Z AM
-40 to 85 8 Ld SOIC (Pb-free)
X5328V14-4.5A
X5329V14-4.5A
0 to 70 14 Ld TSSOP
X5328V14Z-4.5A
(Note)
X5328V Z AL X5329V14Z-4.5A
(Note)
X5329V Z AL
0 to 70
14 Ld TSSOP
(Pb-free)
X5328V14I-4.5A
X5329V14I-4.5A
-40 to 85 14 Ld TSSOP
X5328V14IZ-4.5A
(Note)
X5328V Z AM X5329V14IZ-4.5A
(Note)
X5329V Z AM
-40 to 85 14 Ld TSSOP
(Pb-free)
X5328P
X5328P
X5329P
X5329P
4.5-5.5
4.25-4.5
0 to 70 8 Ld PDIP
X5328PZ (Note)
X5328P Z X5329PZ (Note)
X5329P Z
0 to 70 8 Ld PDIP (Pb-free)
X5328PI
X5328P I
X5329PI
X5329P I
-40 to 85 8 Ld PDIP
X5328PIZ (Note)
X5328P Z I X5329PIZ (Note)
X5329P Z I
-40 to 85 8 Ld PDIP (Pb-free)
X5328S8*
X5328
X5329S8*
0 to 70 8 Ld SOIC
X5328S8Z* (Note) X5328 Z
X5329S8Z* (Note) X5329 Z
0 to 70 8 Ld SOIC (Pb-free)
X5328S8I*
X5328 I
X5329S8I*
-40 to 85 8 Ld SOIC
X5328S8IZ* (Note) X5328 Z I X5329S8IZ* (Note) X5329 Z I
-40 to 85 8 Ld SOIC (Pb-free)
X5328V14*
X5328V
X5329V14*
0 to 70 14 Ld TSSOP
X5328V14Z* (Note) X5328V Z X5329V14Z* (Note) X5329V Z
X5328V14I*
X5328V14IZ* (Note)
X5328V Z I
X5329V14I*
X5329V14IZ* (Note)
X5329V Z I
X5328P-2.7A
X5329P-2.7A
X5328PZ-2.7A (Note) X5328P Z AN X5329PZ-2.7A (Note) X5329P Z AN
X5328PI-2.7A
X5329PI-2.7A
X5328PIZ-2.7A (Note) X5328P Z AP X5329PIZ-2.7A (Note) X5329P Z AP
X5328S8-2.7A
X5328 AN X5329S8-2.7A
X5328S8Z-2.7A (Note) X5328 Z AN X5329S8Z-2.7A (Note) X5329 Z AN
X5328S8I-2.7A
X5328 AP X5329S8I-2.7A
X5328S8IZ-2.7A
(Note)
X5328 Z AP X5329S8IZ-2.7A
(Note)
X5329 Z AP
X5328V14-2.7A
X5328V AN X5329V14-2.7A
X5328V14Z-2.7A
(Note)
X5328V Z AN X5329V14Z-2.7A
(Note)
X5329V Z AN
2.7-5.5
2.85-3.0
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
14 Ld TSSOP
(Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
0 to 70
0 to 70
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
2 FN8132.1
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X5328, X5329
Ordering Information (Continued)
PART NUMBER
RESET
(ACTIVE LOW)
X5328V14I-2.7A
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
X5329V14I-2.7A
PART
MARKING
VCC RANGE
TEMP
(V) VTRIP RANGE RANGE (°C)
PACKAGE
2.7-5.5
2.85-3.0
-40 to 85 14 Ld TSSOP
X5328V14IZ-2.7A
(Note)
X5328V Z AP X5329V14IZ-2.7A
(Note)
X5329V Z AP
-40 to 85 14 Ld TSSOP
(Pb-free)
X5328P-2.7
X5328P F X5329P-2.7
X5329P F
2.7-5.5
2.55-2.7
0 to 70 8 Ld PDIP
X5328PZ-2.7 (Note) X5328P Z F X5329PZ-2.7 (Note) X5329P Z F
0 to 70 8 Ld PDIP (Pb-free)
X5328PI-2.7
X5328P G X5329PI-2.7
X5329P G
-40 to 85 8 Ld PDIP
X5328PIZ-2.7 (Note) X5328P Z G X5329PIZ-2.7 (Note) X5329P Z G
-40 to 85 8 Ld PDIP (Pb-free)
X5328S8-2.7*
X5328 F
X5329S8-2.7*
0 to 70 8 Ld SOIC
X5328S8Z-2.7* (Note) X5328 Z F X5329S8Z-2.7* (Note) X5329 Z F
0 to 70 8 Ld SOIC (Pb-free)
X5328S8I-2.7*
X5328 G
X5329S8I-2.7*
-40 to 85 8 Ld SOIC
X5328S8IZ-2.7* (Note) X5328 Z G X5329S8IZ-2.7* (Note) X5329 Z G
-40 to 85 8 Ld SOIC (Pb-free)
X5328V14-2.7*
X5329V14-2.7*
0 to 70 14 Ld TSSOP
X5328V14Z-2.7*
(Note)
X5328V Z F X5329V14Z-2.7*
(Note)
X5329V Z F
0 to 70
14 Ld TSSOP
(Pb-free)
X5328V14I-2.7*
X5329V14I-2.7*
-40 to 85 14 Ld TSSOP
X5328V14IZ-2.7*
(Note)
X5328V Z G X5329V14IZ-2.7*
(Note)
X5329V Z G
-40 to 85 14 Ld TSSOP
(Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3 FN8132.1
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X5328, X5329
PIN DESCRIPTION
Pin Pin
(SOIC/PDIP) TSSOP
11
22
58
69
36
47
8 14
7 13
3-5,10-12
Name
CS
SO
SI
SCK
WP
VSS
VCC
RESET/
RESET
NC
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The Serial Clock controls the serial bus timing for data input and out-
put. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the Watchdog Timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever VCC falls below the minimum VCC sense level. It
will remain active until VCC rises above the minimum VCC sense level for 200ms.
RESET/RESET goes active on power-up at about 1V and remains active for
200ms after the power supply stabilizes.
No internal connections
PIN CONFIGURATION
CS
SO
WP
VCC
8 Ld SOIC/PDIP
18
27
X5328/29
36
45
VCC
RESET/RESET
SCK
SI
14 Ld TSSOP
CS 1
14
SO 2
NC 3
13
12
NC 4 X5328/29 11
NC 5
10
WP 6
9
VSS 7
8
VCC
RESET/RESET
NC
NC
NC
SCK
SI
4 FN8132.1
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X5328, X5329
PRINCIPLES OF OPERATION
Power-On Reset
Application of power to the X5328/X5329 activates a
Power-on Reset Circuit. This circuit goes active at
about 1V and pulls the RESET/RESET pin active. This
signal prevents the system microprocessor from start-
ing to operate with insufficient voltage or prior to stabi-
lization of the oscillator. When VCC exceeds the device
VTRIP value for 200ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin exe-
cuting code.
Low Voltage Monitoring
During operation, the X5328/X5329 monitors the VCC
level and asserts RESET/RESET if supply voltage
falls below a preset minimum VTRIP. The
RESET/RESET signal prevents the microprocessor
from operating in a power fail or brownout condition.
The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until
VCC returns and exceeds VTRIP for 200ms.
VCC Threshold Reset Procedure
The X5328/X5329 has a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard VTRIP is not exactly right, or
for higher precision in the VTRIP value, the
X5328/X5329 threshold may be adjusted.
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and
the new VTRIP is 4.6V, this procedure directly makes
the change. If the new setting is lower than the current
setting, then it is necessary to reset the trip point
before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the VCC pin and tie the CS pin and the WP
pin HIGH. RESET/RESET and SO pins are left uncon-
nected. Then apply the programming voltage VP to
both SCK and SI and pulse CS LOW then HIGH.
Remove VP and the sequence is complete.
Figure 1. Set VTRIP Voltage
CS
VP
SCK
VP
SI
Resetting the VTRIP Voltage
This procedure sets the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the
VTRIP is reset, the new VTRIP is something less than
1.7V. This procedure must be used to set the voltage
to a lower value.
To reset the VTRIP voltage, apply a voltage between
2.7 and 5.5V to the VCC pin. Tie the CS pin, the WP
pin, and the SCK pin HIGH. RESET/RESET and SO
pins are left unconnected. Then apply the program-
ming voltage VP to the SI pin ONLY and pulse CS
LOW then HIGH. Remove VP and the sequence is
complete.
Figure 2. Reset VTRIP Voltage
CS
SCK VCC
VP
SI
5 FN8132.1
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