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®
Data Sheet
X5323, X5325
(Replaces X25323, X25325)
October 27, 2005
FN8131.1
CPU Supervisor with 32Kb SPI EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence
—Reset signal valid to VCC = 1V
• Determine watchdog or low voltage reset with a
volatile flag bit
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 32Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lockprotection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
DESCRIPTION
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
WP
SI
SO
SCK
CS/WDI
VCC
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset Logic
Watchdog Transition
Detector
Protect Logic
Status
Register
8Kbits
8Kbits
16Kbits
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
X5323 = RESET
X5325 = RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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X5323, X5325
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
X5323P-4.5A
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
X5323P AL X5325P-4.5A
PART
MARKNIG
X5325P AL
VCC RANGE
TEMP
(V) VTRIP RANGE RANGE (°C)
PACKAGE
4.5-5.5
4.5-4.75
0 to 70 8 Ld PDIP
X5323PZ-4.5A (Note) X5323P Z AL X5325PZ-4.5A
X5325P Z AL
0 to 70 8 Ld PDIP (Pb-free)
X5323PI-4.5A
X5323P AM X5325PI-4.5A
X5325P AM
-40 to 85 8 Ld PDIP
X5323PIZ-4.5A (Note) X5323P Z AM X5325PIZ-4.5A
X5325P Z AM
-40 to 85 8 Ld PDIP (Pb-free)
X5323S8-4.5A
X5323 AL X5325S8-4.5A
X5325 AL
0 to 70 8 Ld SOIC
X5323S8Z-4.5A (Note) X5323 Z AL X5325S8Z-4.5A (Note) X5325 Z AL
0 to 70 8 Ld SOIC (Pb-free)
X5323S8I-4.5A*
X5323 AM X5325S8I-4.5A
X5325 AM
-40 to 85 8 Ld SOIC
X5323S8IZ-4.5A*
(Note)
X5323 Z AM X5325S8IZ-4.5A
(Note)
X5325 Z AM
-40 to 85 8 Ld SOIC (Pb-free)
X5323V14-4.5A
X5325V14-4.5A
0 to 70 14 Ld TSSOP
X5323V14Z-4.5A
(Note)
X5323V Z AL X5325V14Z-4.5A
(Note)
X5325V Z AL
0 to 70 14 Ld TSSOP
(Pb-free)
X5323V14I-4.5A
X5325V14I-4.5A
-40 to 85 14 Ld TSSOP
X5323V14IZ-4.5A
(Note)
X5323V Z AM X5325V14IZ-4.5A
(Note)
X5325V Z AM
-40 to 85 14 Ld TSSOP
(Pb-free)
X5323P
X5323P
X5325P
X5325P
4.5-5.5
4.25-4.5
0 to 70 8 Ld PDIP
X5323PZ (Note)
X5323P Z X5325PZ
X5325P Z
0 to 70 8 Ld PDIP (Pb-free)
X5323PI
X5323P I
X5325PI
X5325P I
-40 to 85 8 Ld PDIP
X5323PIZ (Note)
X5323P Z I X5325PIZ
X5325P Z I
-40 to 85 8 Ld PDIP (Pb-free)
X5323S8*
X5323
X5325S8*
X5325
0 to 70 8 Ld SOIC
X5323S8Z* (Note)
X5323 Z
X5325S8Z* (Note)
X5325 Z
0 to 70 8 Ld SOIC (Pb-free)
X5323S8I*
X5323 I
X5325S8I*
X5325 I
-40 to 85 8 Ld SOIC
X5323S8IZ* (Note) X5323 Z I X5325S8IZ* (Note) X5325 Z I
-40 to 85 8 Ld SOIC (Pb-free)
X5323V14*
X5323V
X5325V14*
0 to 70 14 Ld TSSOP
X5323V14Z* (Note) X5323V Z X5325V14Z* (Note) X5325V Z
X5323V14I*
X5323V14IZ* (Note)
X5323V Z I
X5325V14I*
X5325V14IZ* (Note)
X5325V Z I
X5323P-2.7A
X5323P AN X5325P-2.7A
X5325P AN
X5323PZ-2.7A (Note) X5323P Z AN X5325PZ-2.7A
X5325P Z AN
X5323PI-2.7A
X5323P AP X5325PI-2.7A
X5325P AP
X5323PIZ-2.7A (Note) X5323P Z AP X5325PIZ-2.7A
X5325P Z AP
X5323S8-2.7A*
X5323 AN X5325S8-2.7A
X5325 AN
X5323S8Z-2.7A*
(Note)
X5323 Z AN X5325S8Z-2.7A (Note) X5325 Z AN
X5323S8I-2.7A*
X5323 AP X5325S8I-2.7A
X5325 AP
X5323S8IZ-2.7A*
(Note)
X5323 Z AP X5325S8IZ-2.7A
(Note)
X5325 Z AP
2.7-5.5
2.85-3.0
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
14 Ld TSSOP
(Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
-40 to 85 8 Ld SOIC
-40 to 85 8 Ld SOIC (Pb-free)
2 FN8131.1
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X5323, X5325
Ordering Information (Continued)
PART NUMBER
RESET
(ACTIVE LOW)
X5323V14-2.7A
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
X5323V AN X5325V14-2.7A
PART
MARKNIG
VCC RANGE
TEMP
(V) VTRIP RANGE RANGE (°C)
PACKAGE
2.7-5.5
2.85-3.0
0 to 70 14 Ld TSSOP
X5323V14Z-2.7A
(Note)
X5323V Z AN X5325V14Z-2.7A
(Note)
X5325V Z AN
0 to 70 14 Ld TSSOP
(Pb-free)
X5323V14I-2.7A
X5325V14I-2.7A
-40 to 85 14 Ld TSSOP
X5323V14IZ-2.7A
(Note)
X5323V Z AP X5325V14IZ-2.7A
(Note)
X5325V Z AP
-40 to 85 14 Ld TSSOP
(Pb-free)
X5323P-2.7
X5323P F X5325P-2.7
X5325P F
2.7-5.5
2.55-2.7
0 to 70 8 Ld PDIP
X5323PZ-2.7 (Note) X5323P Z F X5325PZ-2.7
X5325P Z F
0 to 70 8 Ld PDIP (Pb-free)
X5323PI-2.7
X5323P G X5325PI-2.7
X5325P G
-40 to 85 8 Ld PDIP
X5323PIZ-2.7 (Note) X5323P Z G X5325PIZ-2.7
X5325P Z G
-40 to 85 8 Ld PDIP (Pb-free)
X5323S8-2.7*
X5323 F
X5325S8-2.7*
X5325 F
0 to 70 8 Ld SOIC
X5323S8Z-2.7* (Note) X5323 Z F X5325S8Z-2.7* (Note) X5325 Z F
0 to 70 8 Ld SOIC (Pb-free)
X5323S8I-2.7*
X5323 G
X5325S8I-2.7*
X5325 G
-40 to 85 8 Ld SOIC
X5323S8IZ-2.7* (Note) X5323 Z G X5325S8IZ-2.7* (Note) X5325 Z G
-40 to 85 8 Ld SOIC (Pb-free)
X5323V14-2.7*
X5325V14-2.7*
X5325V F
0 to 70 14 Ld TSSOP
X5323V14Z-2.7*
(Note)
X5323V Z F X5325V14Z-2.7*
(Note)
X5325V Z F
0 to 70 14 Ld TSSOP
(Pb-free)
X5323V14I-2.7*
X5325V14I-2.7*
-40 to 85 14 Ld TSSOP
X5323V14IZ-2.7*
(Note)
X5323V Z G X5325V14IZ-2.7*
(Note)
X5325V Z G
-40 to 85 14 Ld TSSOP
(Pb-free)
*Add "-T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3 FN8131.1
October 27, 2005

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PIN CONFIGURATION
X5323, X5325
CS/WDT
SO
WP
VSS
8 Ld SOIC/PDIP
18
X5323/25
27
36
45
VCC
RESET/RESET
SCK
SI
CS/WDT
SO
NC
NC
NC
WP
VSS
14 Ld TSSOP
1 14
2 13
3 12
4 X5323/25 11
5 10
69
78
VCC
RESET/RESET
NC
NC
NC
SCK
SI
PIN DESCRIPTION
Pin
(SOIC/PDIP)
1
Pin
TSSOP
1
22
58
69
36
47
8 14
7 13
3-5,10-12
Name
CS/WDI
SO
SI
SCK
WP
VSS
VCC
RESET/
RESET
NC
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a
high impedance state. Unless a nonvolatile write cycle is underway, the
device will be in the standby power mode. CS LOW enables the device, placing
it in the active power mode. Prior to the start of any operation after power-up, a
HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The serial clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or data bits present
on the SI pin. The falling edge of SCK changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever VCC falls below the minimum VCC sense level. It will re-
main active until VCC rises above the minimum VCC sense level for 200ms. RE-
SET/RESET goes active if the watchdog timer is enabled and CS
remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes
active on power-up at about 1V and remains active for 200ms after the power
supply stabilizes.
No internal connections
4 FN8131.1
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X5323, X5325
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X5323/X5325 activates a
power-on reset circuit. This circuit goes active at about
1V and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. As long as RESET/RESET pin is
active, the device will not respond to any Read/Write
instruction. When VCC exceeds the device VTRIP value
for 200ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin exe-
cuting code.
Low Voltage Monitoring
During operation, the X5323/X5325 monitors the VCC
level and asserts RESET/RESET if supply voltage
falls below a preset minimum VTRIP. The
RESET/RESET signal prevents the microprocessor
from operating in a power fail or brownout condition.
The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until
VCC returns and exceeds VTRIP for 200ms.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET/RESET signal. The CS/WDI pin must be tog-
gled from HIGH to LOW prior to the expiration of the
watchdog time out period. The state of two nonvolatile
control bits in the status register determine the watch-
dog timer period. The microprocessor can change
these watchdog bits, or they may be “locked” by tying
the WP pin LOW and setting the WPEN bit HIGH.
VCC Threshold Reset Procedure
The X5323/X5325 has a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard VTRIP is not exactly right, or
for higher precision in the VTRIP value, the
X5323/X5325 threshold may be adjusted.
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and
the new VTRIP is 4.6V, this procedure directly makes
the change. If the new setting is lower than the current
setting, then it is necessary to reset the trip point
before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the Vcc pin and tie the CS/WDI pin and
the WP pin HIGH. RESET/RESET and SO pins are
left unconnected. Then apply the programming voltage
VP to both SCK and SI and pulse CS/WDI LOW then
HIGH. Remove VP and the sequence is complete.
Figure 1. Set VTRIP Voltage
CS
VP
SCK
VP
SI
Resetting the VTRIP Voltage
This procedure sets the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the
VTRIP is reset, the new VTRIP is something less than
1.7V. This procedure must be used to set the voltage
to a lower value.
To reset the VTRIP voltage, apply a voltage between
2.7 and 5.5V to the VCC pin. Tie the CS/WDI pin, the
WP pin, and the SCK pin HIGH. RESET/RESET and
SO pins are left unconnected. Then apply the pro-
gramming voltage VP to the SI pin ONLY and pulse
CS/WDI LOW then HIGH. Remove VP and the
sequence is complete.
Figure 2. Reset VTRIP Voltage
CS
SCK VCC
VP
SI
5 FN8131.1
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