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Intel386™ SXSA
EMBEDDED MICROPROCESSOR
Static Intel386™ CPU Core
— Low Power Consumption
— Operating Power Supply
4.5V to 5.5V - 25 and 33 MHz
4.75V to 5.25V - 40 MHz
— Operating Frequency
SA-40 = 40 MHz
SA-33 = 33 MHz
SA-25 = 25 MHz
Clock Freeze Mode Allows Clock
Stopping at Any Time
Full 32-bit Internal Architecture
— 8-, 16-, 32-bit Data Types
— 8 General Purpose 32-bit Registers
Runs Intel386 Architecture Software in
a Cost-effective, 16-bit Hardware
Environment
— Runs Same Applications and
Operating Systems as the Intel386
SX and Intel386 DX Processors
— Object Code Compatible with 8086,
80186, 80286, and Intel386
Processors
TTL-Compatible Inputs
High-performance 16-bit Data Bus
— Two-clock Bus Cycles
— Address Pipelining Allows Use of
Slower, Inexpensive Memories
Integrated Memory Management Unit
(MMU)
— Virtual Memory Support
— Optional On-chip Paging
— 4 Levels of Hardware-Enforced
Protection
— MMU Fully Compatible with 80286
and Intel386 DX Processors
Virtual 8086 Mode Allows Execution of
8086 Software in a Protected and Paged
System
Large Uniform Address Space
— 16 Megabyte Physical
— 64 Terabyte Virtual
— 4 Gigabyte Maximum Segment Size
Numerics Support Intel387™ SX and
Intel387™ SL Math Coprocessors
On-chip Debugging Support Including
Breakpoint Registers
Complete System Development
Support
High Speed CHMOS Technology
100-Pin Plastic Quad Flatpack Package
The Intel386™ SXSA embedded microprocessor is a 5-volt, 32-bit, fully static CPU with a 16-bit external data
bus and a 24-bit external address bus. The Intel386 SXSA CPU brings the vast software library of the Intel386
architecture to embedded systems. It provides the performance benefits of 32-bit programming with the cost
msavings associated with 16-bit hardware systems.
.coThe Intel386 SXSA microprocessor is manufactured on Intel’s 0.8-micron CHMOS V process. This process
provides high performance and low power consumption for power-sensitive applications. Figure 3 and Figure 4
uillustrate the flexibility of low power devices with respect to temperature and frequency relationships.
tasheet4Information in this document is provided solely to enable use of Intel products. Intel assumes no liability
awhatsoever, including infringe-ment of any patent or copyright, for sale and use of Intel products except as
.dprovided in Intel’s Terms and Conditions of Sale for such products. Information contained herein supersedes
previously published specifications on these devices from Intel.
www Copyright© INTEL Corporation, 2002
June 2002
Order Number: 272419-004

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Intel386™ SXSA EMBEDDED MICROPROCESSOR
Effective Address Bus
Segmentation Unit
32 3-Input
Adder
32
Effective Address Bus
Descriptor 32
Register
Paging Unit
Adder
Page Cache
Bus Control
Request
Prioritizer
Protection
Test Unit
Limit and
Attribute
PLA
Internal Control Bus
Control and
Attribute
PLA
27
Address
Driver
Pipeline/
Bus Size
Control
32
Barrel
Shifter/
Adder Status
Multiply/ Flags
Divide
Register
File
ALU
Control
ALU
Decode
and
Sequencing
Control
ROM
Control
Instruction
Decoder
3-Decoded
Instruction
Queue
Instruction
Predecode
Code
Stream
32
Prefetcher/
Limit
Checker
16-Byte
Code
Queue
Instruction
Prefetch
Dedicated ALU Bus
MUX/
Trans-
ceivers
32
HOLD,
RESET
INTR, NMI
ERROR#
BUSY#,HLDA
BLE#, BHE#
A23:1
M/IO#, D/C#
W/R#, LOCK#
ADS#, NA#
READY#
D15:0
A2298-01
Figure 1. Intel386™ SXSA Microprocessor Block Diagram
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1.0 PIN ASSIGNMENT
Intel386™ SXSA EMBEDDED MICROPROCESSOR
D0
Vss
HLDA
HOLD
Vss
NA#
READY#
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
CLK2
ADS#
BLE#
A1
BHE#
NC
Vcc
Vss
M/IO#
D/C#
W/R#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TOP VIEW
75 A20
74 A19
73 A18
72 A17
71 Vcc
70 A16
69 Vcc
68 Vss
67 Vss
66 A15
65 A14
64 A13
63 Vss
62 A12
61 A11
60 A10
59 A9
58 A8
57 Vcc
56 A7
55 A6
54 A5
53 A4
52 A3
51 A2
NOTE:
NC = No Connection
Figure 2. Intel386™ SXSA Microprocessor Pin Assignment (PQFP)
A2297-0A
3

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Intel386™ SXSA EMBEDDED MICROPROCESSOR
Pin Symbol
1 D0
2 VSS
3 HLDA
4 HOLD
5 VSS
6 NA#
7 READY#
8 VCC
9 VCC
10 VCC
11 VSS
12 VSS
13 VSS
14 VSS
15 CLK2
16 ADS#
17 BLE#
18 A1
19 BHE#
20 NC
21 VCC
22 VSS
23 M/IO#
24 D/C#
25 W/R#
Table 1. Pin Assignment
Pin
Symbol
Pin
Symbol
26 LOCK#
51 A2
27 NC
52 A3
28 FLT#
53 A4
29 NC
54 A5
30 NC
55 A6
31 NC
56 A7
32 VCC
33 RESET
57 VCC
58 A8
34 BUSY#
59 A9
35 VSS
36 ERROR#
60 A10
61 A11
37 PEREQ
62 A12
38 NMI
39 VCC
40 INTR
63 VSS
64 A13
65 A14
41 VSS
42 VCC
43 NC
44 NC
45 NC
66 A15
67 VSS
68 VSS
69 VCC
70 A16
46 NC
47 NC
71 VCC
72 A17
48 VCC
49 VSS
50 VSS
73 A18
74 A19
75 A20
Pin Symbol
76 A21
77 VSS
78 VSS
79 A22
80 A23
81 D15
82 D14
83 D13
84 VCC
85 VSS
86 D12
87 D11
88 D10
89 D9
90 D8
91 VCC
92 D7
93 D6
94 D5
95 D4
96 D3
97 VCC
98 VSS
99 D2
100 D1
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Intel386™ SXSA EMBEDDED MICROPROCESSOR
2.0 PIN DESCRIPTIONS
Table 2 lists the Intel386 SXSA microprocessor pin descriptions. The following definitions are used in the pin
descriptions:
# The named signal is active low.
I Input signal.
O Output signal.
I/O Input and output signal.
P Power pin.
G Ground pin.
Table 2. Pin Descriptions
Symbol
Type Pin
Name and Function
A23:1
O 80–79, 76–72, Address Bus outputs physical memory or port I/O addresses.
70, 66–64
62–58, 56–51,
18
ADS#
O 16
Address Status indicates that the processor is driving a valid
bus-cycle definition and address onto its pins (W/R#, D/C#,
M/IO#, BHE#, BLE#, and A23:1).
BHE#
O 19
Byte High Enable indicates that the processor is transferring
a high data byte.
BLE#
O 17
Byte Low Enable indicates that the processor is transferring
a low data byte.
BUSY#
I
34
Busy indicates that the math coprocessor is busy.
CLK2 I 15
CLK2 provides the fundamental timing for the device.
D/C#
O 24
Data/Control indicates whether the current bus cycle is a
data cycle (memory or I/O) or a control cycle (interrupt
acknowledge, halt, or code fetch). When D/C# is high, the bus
cycle is a data cycle; when D/C# is low, the bus cycle is a con-
trol cycle.
D15:0
I/O 81–83, 86–90, Data Bus inputs data during memory read, I/O read, and
92–96, 99–100, interrupt acknowledge cycles and outputs data during mem-
1 ory and I/O write cycles.
ERROR# I
36
Error indicates that the math coprocessor has an error condi-
tion.
FLT# I 28
Float forces all bidirectional and output signals, including
HLDA, to a high-impedance state.
HLDA
O3
Bus Hold Acknowledge indicates that the CPU has surren-
dered control of its local bus to another bus master.
HOLD
I
4
Bus Hold Request allows another bus master to request con-
trol of the local bus.
INTR I 40
Interrupt Request is a maskable input that causes the CPU
to suspend execution of the current program and then exe-
cute an interrupt acknowledge cycle.
5