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®
PRELIMINARY
Data Sheet
July 22, 2005
ISL6548A
FN9189.1
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6548A provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply VDDQ during S0/S1 and S3 states. During S0/S1
state, a fully integrated sink-source regulator generates an
accurate (VDDQ/2) high current VTT voltage without the
need for a negative supply. A second PWM controller, which
requires external MOSFET drivers, is available for regulation
of the GMCH Core voltage. A sink/source LDO controller is
also integrated for the CPU/GMCH VTT termination voltage
regulation. Another LDO is available for the ICH7 voltage.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH and CPU VTT termination voltage
is within spec and operational.
All outputs, except VICH7, have undervoltage protection. The
switching regulator also has overvoltage and overcurrent
protection. Thermal shutdown is integrated.
Features
• Generates 5 Regulated Voltages
- Synchronous Buck PWM Controller for DDR VDDQ
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR VTT
- PWM Regulator for GMCH Core
- Sink/Source LDO Regulator for CPU/GMCH VTT
Termination
- LDO Regulator for ICH7
• ACPI compliant sleep state control
• Glitch-free Transitions During State Changes
• VDDQ PWM Controller Drives Low Cost N-Channel
MOSFETs
• 250kHz Constant Frequency Operation
- Both PWM controllers are Phase Shifted 180°
• Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring
• OCP on the VDDQ Switching Regulator
• Integrated Thermal Shutdown Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL6548A
Ordering Information
PART
NUMBER
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6548ACRZ
(Note)
0 to 70 28 Ld 6x6 QFN (Pb-free) L28.6x6
ISL6548ACRZ-T
(Note)
0 to 70 28 Ld 6x6 QFN (Pb-free) L28.6x6
Tape and Reel
ISL6548ACRZA
(Note)
0 to 70 28 Ld 6x6 QFN (Pb-free) L28.6x6
ISL6548ACRZA-T
(Note)
0 to 70
28 Ld 6x6 QFN (Pb-free) L28.6x6
Tape and Reel
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinout
ISL6548A (QFN)
TOP VIEW
28 27 26 25 24 23 22
5VSBY 1
21 DRIVE3
S3# 2
20 FB3
P12V 3
GND 4
DDR_VTT 5
GND
29
19 PWM4
18 FB4
17 COMP4
DDR_VTT 6
16 COMP
VDDQ 7
15 FB
8 9 10 11 12 13 14
2 FN9189.1
July 22, 2005

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Block Diagram
PWM4
COMP4
FB4
EA4
DRIVE2_U
FB2
P12V
EA2
DRIVE2_L
DRIVE3
FB3
P12V
EA3
180°
PHASE
SHIFT
5VSBY
P12V
S3# S5#
FB
COMP
POR
EA1
MONITOR AND CONTROL
SOFT-START & ENABLE A
SOFT-START & ENABLE B
SOFT-START & ENABLE C
ENABLE DDR_VTT
ENABLE VIDPGD
VOLTAGE
REFERENCE
0.800V
0.680V (-15%)
0.920V (+15%)
EA1 ACTIVE
IN S3
FAULT
S3
UV
UV/OV
UV
UV/OV
250kHz
OSCILLATOR
PWM
5VSBY
BOOT
UGATE
LGATE
OC
COMP 20µA
PHASE
OCSET
VTT
REG
RL
VTTSNS
VDDQ(2)
VTT(2)
RU
VREF_IN
VIDPGD
GND PAD
GND(2)

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ISL6548A
Simplified Power System Diagram
5VSBY
12V
3V3ATX
VGMCH
+
Q3
Q4
SLP_S3
SLP_S5
SLEEP
STATE
LOGIC
PWM
CONTROLLER
ISL6548A
PWM
CONTROLLER
Q5
VTT_GMCH/CPU
+
Q6
VTT
REGULATOR
LINEAR
CONTROLLER
LINEAR
CONTROLLER
5VDUAL
Q1
VDDQ
+
Q2
3V3ATX or VGMCH
Q7
+
VREF
VTT
+
VICH7
Typical Application
3VDUAL
5VSBY 12V
5VDUAL
VGMCH
VTT_GMCH/CPU
ATX3V3
SLP_S5
SLP_S3
VIDPGD
S5#
S3#
BOOT
OCSET
ISL6548A
UGATE
Q3
PHASE
PWM4
Q4
R5
C7 R7
Q5
C5
C6 R6
R8
R9
R10
COMP4
FB4
DRIVE2_U
FB2
Q6 DRIVE2_L
LGATE
DDR_VDDQ(x2)
COMP
FB
VREF_IN
DDR_VTT(x2)
DDR_VTTSNS
DRIVE3
FB3
DBOOT
ROCSET
CBOOT
C1
R2 C2
Q1
VDDQ_DDR
+
Q2
R3 C3
R1
R4
ATX3V3 or VGMCH
VTT_DDR
Q7
R11
R12
VICH7
4 FN9189.1
July 22, 2005

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ISL6548A
Absolute Maximum Ratings
5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V
All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
QFN Package . . . . . . . . . . . . . . . . . . .
32
4
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
5VSBY SUPPLY CURRENT
Nominal Supply Current
POWER-ON RESET
ICC_S0
ICC_S5
S3# & S5# HIGH, UGATE/LGATE Open
5.5 7.0 8.0
S5# LOW, S3# Don’t Care, UGATE/LGATE Open -
700 850
mA
µA
Rising 5VSBY POR Threshold
4.10 - 4.45
V
Falling 5VSBY POR Threshold
3.60 - 3.95
V
Rising P12V POR Threshold
10.0 - 10.5
V
Falling P12V POR Threshold
8.80 - 9.75
V
OSCILLATOR AND SOFT-START
PWM Frequency
Ramp Amplitude
Soft-Start Interval
REFERENCE VOLTAGE
fOSC
VOSC
tSS
220 250 280
- 1.5 -
6.5 8.2 9.5
kHz
V
ms
Reference Voltage
System Accuracy
VREF
- 0.800 -
-2.0 - +2.0
V
%
VDDQ AND VGMCH PWM CONTROLLER ERROR AMPLIFIERS
DC Gain
Guaranteed By Design
- 80 -
dB
Gain-Bandwidth Product
GBWP
15 -
- MHz
Slew Rate
SR
- 6 - V/µs
CONTROL I/O (S3#, S5#)
LOW Level Input Threshold
0.75 -
-
V
HIGH Level Input Threshold
- - 2.2 V
5 FN9189.1
July 22, 2005