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®
Data Sheet
February 9, 2005
ISL6548
FN9188.1
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6548 provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply VDDQ during S0/S1 and S3 states. During S0/S1
state, a fully integrated sink-source regulator generates an
accurate (VDDQ/2) high current VTT voltage without the
need for a negative supply. Two LDO controllers are also
integrated for the GMCH core voltage regulation and for the
GMCH/CPU VTT termination voltage regulation.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH/CPU VTT termination voltage is
within spec and operational.
Each output is monitored for undervoltage events. The
switching regulator also has overvoltage and overcurrent
protection. Thermal shutdown is integrated.
Pinout
ISL6548 (6x6 QFN)
TOP VIEW
28 27 26 25 24 23 22
5VSBY 1
21 DRIVE4
S3# 2
20 REFADJ4
P12V 3
GND 4
DDR_VTT 5
GND
29
19 DRIVE3
18 FB3
17 FB4
DDR_VTT 6
16 COMP
VDDQ 7
15 FB
8 9 10 11 12 13 14
Features
• Generates 4 Regulated Voltages
- Synchronous Buck PWM Controller for DDR VDDQ
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR VTT
- LDO Regulator for GMCH Core
- Sink/Source LDO Regulator for CPU/GMCH VTT
Termination
• ACPI compliant sleep state control
• Glitch-free Transitions During State Changes
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring on All Outputs
• OCP on the Switching Regulator
• Integrated Thermal Shutdown Protection
• Pb-Free Available (RoHS Compliant)
Applications
Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6548CRZ
(Note)
0 to 70 28 Ld 6x6 QFN (Pb-free) L28.6x6
ISL6548CRZ-T
(Note)
0 to 70 28 Ld 6x6 QFN
L28.6x6
Tape and Reel (Pb-free)
ISL6548CRZ A
(Note)
0 to 70 28 Ld 6x6 QFN (Pb-free) L28.6x6
ISL6548CRZA-T
(Note)
0 to 70 28 Ld 6x6 QFN
L28.6x6
Tape and Reel (Pb-free)
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which are
RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
DRIVE4
FB4
REFADJ4
DRIVE3
FB3
DRIVE2_U
FB2
DRIVE2_L
P12V
EA4
P12V
EA3
P12V
EA2
P12V
5VSBY
P12V
VDDQ
RGU
GMCH DUAL LDO
RGL
POR
S3# S5#
FB COMP
EA1
PWM
5VSBY
MONITOR AND CONTROL
SOFTSTART & ENABLE A
SOFTSTART & ENABLE B
SOFTSTART & ENABLE C
ENABLE VIDPGD
ENABLE DDR_VTT
VOLTAGE
REFERENCE
0.800V
0.680V (-15%)
0.920V (+15%)
UV/OV
UV
UV
UV/OV
FAULT
S3
OSCILLATOR
250kHz
OC
COMP 20µA
VTT
REG
RU
RL
BOOT
UGATE
LGATE
PHASE
OCSET
VTTSNS
VDDQ(2)
VTT(2)
VREF_IN
VIDPGD
GND PAD
GND(2)

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ISL6548
Simplified Power System Diagram
5VSBY
12V
VDDQ
SLP_S3
SLP_S5
Q3
VGMCH
Q4
+
SLEEP
STATE
LOGIC
TWO STAGE
LINEAR
CONTROLLER
PWM
CONTROLLER
ISL6548
VTT_GMCH/CPU
+
Q5
Q6
LINEAR
CONTROLLER
VTT
REGULATOR
5VDUAL
Q1
VDDQ
+
Q2
VREF
VTT
+
Typical Application
5VSBY 12V
5VDUAL
VDDQ_DDR
Q3
SLP_S5
SLP_S3
VGMCH
Q4
R5
R6
Q5
VTT_GMCH/CPU
R7
R8
Q6
VIDPGD
S5#
S3#
DRIVE4
FB4
REFADJ4
DRIVE3
FB3
BOOT
ISL6548
OCSET
UGATE
PHASE
LGATE
DDR_VDDQ(x2)
COMP
DRIVE2_U
FB
DBOOT
ROCSET
CBOOT
C1
R2 C2
R4
Q1
Q2
R3 C3
R1
VDDQ_DDR
+
FB2
DRIVE2_L
GND
VREF_IN
DDR_VTT(x2)
DDR_VTTSNS
VTT_DDR
3 FN9188.1
February 9, 2005

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ISL6548
Absolute Maximum Ratings
5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V
All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
QFN Package (Notes 1, 2) . . . . . . . . .
32
4
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
5VSBY SUPPLY CURRENT
Nominal Supply Current
POWER-ON RESET
ICC_S0
ICC_S5
S3# & S5# HIGH, UGATE/LGATE Open
5.50
S5# LOW, S3# Don’t Care, UGATE/LGATE Open -
7.00
700
8.00
850
mA
µA
Rising 5VSBY POR Threshold
4.10 - 4.45
V
Falling 5VSBY POR Threshold
3.60 - 3.95
V
Rising P12V POR Threshold
10.0 - 10.5
V
Falling P12V POR Threshold
8.80 - 9.75
V
OSCILLATOR AND SOFT-START
PWM Frequency
Ramp Amplitude
Soft-Start Interval
REFERENCE VOLTAGE
fOSC
VOSC
tSS
220 250 280
- 1.5 -
6.5 8.2 9.5
kHz
V
ms
Reference Voltage
System Accuracy
VREF
- 0.800 -
-2.0 - +2.0
V
%
VDDQ PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Guaranteed By Design
- 80 -
dB
Gain-Bandwidth Product
GBWP
15 -
- MHz
Slew Rate
SR
- 6 - V/µs
CONTROL I/O (S3# and S5#)
Low Level Input Threshold
0.75 -
-
V
High Level Input Threshold
-
- 2.2
V
4 FN9188.1
February 9, 2005

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ISL6548
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source
UGATE and LGATE Sink
VTT REGULATOR
IGATE
IGATE
- -0.8 -
- 0.8 -
A
A
Upper Divider Impedance
Lower Divider Impedance
Maximum VTT Load Current
RU - 2.5 -
RL - 2.5 -
IVTT_MAX Periodic load applied with 30% duty cycle and
-3
-
3
10ms period using ISL6548_6506EVAL1
evaluation board (see Application Note AN1123)
k
k
A
LINEAR REGULATORS
DC GAIN
Guaranteed By Design
- 80 -
dB
Gain Bandwidth Product
GBWP
15 -
- MHz
Slew Rate
SR
- 6 - V/µs
DRIVEn High Output Voltage
DRIVEn unloaded
9.75 10.0
-
V
DRIVEn Low Output Voltage
- 0.16 0.50
V
DRIVEn High Output Source Current
DRIVEn Low Output Sink Current
VIDPGD
VFB = 770mV; VDRIVEn = 0V
VFB = 830mV; VDRIVEn = 10V
- 1.7 2.6 mA
- 1.2 1.75 mA
VTT_GMCH/CPU Rising Threshold
VTT_GMCH/CPU Falling Threshold
PROTECTION
S0
S0
0.725 0.74
-
- 0.70 0.715
V
V
OCSET Current Source
VTT_DDR Current Limit
VDDQ OV Level
VDDQ UV Level
VTT_DDR OV Level
VTT_DDR UV Level
VGMCH UV Level
VTT_GMCH/CPU UV Level
Thermal Shutdown Limit
IOCSET
By Design
VFB/VREF
VFB/VREF
VTT/VVREF_IN
VTT/VVREF_IN
VFB4/VREF
VFB2/VREF
TSD
S0/S3
S0/S3
S0
S0
S0
S0
By Design
18 20 22
-3.3 - 3.3
- 115 -
- 85 -
- 115 -
- 85 -
- 85 -
- 85 -
- 140 -
µA
A
%
%
%
%
%
%
°C
5 FN9188.1
February 9, 2005