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EtherMap-3 Plus Device
OC-3 Ethernet over SONET Mapper
with Rapid Restoration
TXC-04236
DATA SHEET
FEATURES
• Eight 10/100 Mbit/s Ethernet ports, each using a SMII
interface
• Single 1000 Mbit/s Ethernet port, using a parallel GMII
interface (lead shared with SMII interfaces)
• Ethernet Management interface for control and configuration
of externally connected PHYs
• Provides IEEE 802.3 Half Duplex mode on 10/100 Mbit/s
and Full Duplex mode on 10/100/1000 Mbit/s Ethernet ports
• Provides IEEE 802.3 Management Statistics (RMON)
• Ethernet frame encapsulation/decapsulation protocols:
• ITU-T G.7041, Generic Framing Procedure (GFP)
• ITU-T X.86/X.85, Link Access Procedure SDH (LAPS)
• ITU-T Q.922, Link Access Procedure Frame Mode (LAPF)
• RFC1662/3518, PPP Bridging Control Protocol (BCP)
• Performs mapping/demapping of encapsulated Ethernet
frames into/from low order (VT1.5 SPE/VT2 SPE/VC-11/VC-
12) and high order (STS-1 SPE/VC-3) virtually concatenated
payloads
• Performs mapping/demapping of encapsulated Ethernet
frames into/from a single contiguous concatenated (STS-3c-
SPE/VC-4) payload or a single Low/High order
(VT1.5/VT2/VC-11/VC-12/STS-1/VC-3) payload
• Dynamic bandwidth allocation using on-chip LCAS
processing (ITU-T G.7042) for low and high order virtual
concatenated payloads
• Glueless memory interface to external 64/128/256 Mbit
SDRAMs
• Low Order POH and Pointer processing for 84/63
VT1.5/VT2/TU-11/TU-12 and 3 TU-3
• High Order POH processing for STS-1 SPE/VC-3/STS-3c
SPE/VC-4
• Byte-wide 19 MHz parallel Add and Drop Telecom Bus
interfaces
• Per-port Ethernet side and SONET/SDH system side
loopback for system level diagnostics
• 16-bit wide microprocessor interface, selectable between
Motorola or Intel
• Boundary scan (IEEE 1149.1 standard)
• + 3.3V and +1.8V power supplies, 5V tolerant I/O leads
• 400-lead plastic ball grid array package
(PBGA, 27 mm x 27 mm)
• Device Driver
DESCRIPTION
The EtherMap-3 Plus is a highly integrated EoS device that provides for
mapping of 10/100/1000 Mbit/s Ethernet into SONET/SDH STS-3/STM-1
Transport payloads. The device supports connection for up to eight 10/100
Mbit/s Ethernet ports, using SMII interfaces, or a single 1000 Mbit/s
Ethernet port, using a GMII interface. Ethernet frames are encapsulated
using either GFP, LAPS, LAPF or PPP/BCP protocol. The encapsulated
Ethernet frames are then mapped into either virtually concatenated low or
high order payloads, such as VT1.5 SPE/VT2 SPE/VC-11/VC-12/STS-1
SPE/VC-3, or into contiguously concatenated payloads such as STS-3c
SPE/VC-4. Low and high order SONET/SDH POH generation and
processing/termination is performed. A byte-wide parallel interface
Telecom Bus format provides the SONET/SDH interface and may support
either Drop bus or Add bus timing modes.
In addition to support for full-rate Ethernet transfer, over-subscribed
Ethernet transfers are also supported using back pressure mechanisms
(half and full duplex flow control) in order to prevent frame loss. External
SDRAM is used for buffering Ethernet frames to support bandwidth
oversubscription and flow control operation as well as receive
SONET/SDH container alignment and differential delay compensation of
low and high order virtually concatenated payloads.
For both low and high order virtually concatenated payloads, optional on-
chip standards based LCAS processing is provided to allow hitless
dynamic bandwidth adjustments.
A powerful hardware and RTOS independent EtherMap device driver
provides full access to all the features of the device through APIs. It utilizes
matched get/set functions and can be easily ported.
APPLICATIONS
• SONET/SDH add/drop and terminal multiplexers
• Multi-service access platforms (MSAP)
• Compact Access or CPE platforms
• IP DSLAMS
• Wireless Backhaul Electronics (RNC/BSC)
TELECOM BUS SIDE
+1.8V
+3.3V
HO/LO HO/LO
RING POH
Ports Ports
Controls
CLOCKS
(SONET/SDH Ref,
System, One Sec.)
ETHERNET LINE SIDE
EtherMap-3 Plus
10/100 Mbit/s SMII (Port 1)
DROP Bus
.comADD Bus
OC-3 Ethernet over
SONET Mapper
with Rapid Restoration
TXC-04236
/ 1000 Mbit/s GMII
10/100 Mbit/s SMII (Port 8)
eet4u Microprocessor SDRAM
h Interface Interface
sU.S. and/or foreign patents issued or pending
taCopyright © 2004 TranSwitch Corporation
EtherMap, PHAST, TEMx28, TranSwitch and TXC
aare registered trademarks of TranSwitch Corporation
Boundary
Scan
Ethernet
Management
Interface
Document Number:
PRELIMINARY TXC-04236-MB, Ed. 3
July 2004
.d TranSwitch Corporation 3 Enterprise Drive Shelton, Connecticut 06484 USA
www Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com

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Proprietary TranSwitch Corporation Information for use Solely by its Customers
EtherMap-3 Plus
TXC-04236
DATA SHEET
TABLE OF CONTENTS
Section
Page
List of Figures ........................................................................................................................................................... 6
List of Tables ............................................................................................................................................................ 8
Features ................................................................................................................................................................. 15
Mappings ........................................................................................................................................................... 15
Encapsulation Protocols .................................................................................................................................... 15
Ethernet Ports .................................................................................................................................................... 16
10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) Block ................................................................ 16
SDRAM Interface ............................................................................................................................................... 16
Telecom Bus Timing .......................................................................................................................................... 16
Alarm Indication Port Interface .......................................................................................................................... 17
POH Port Interface ............................................................................................................................................ 17
Microprocessor Interface ................................................................................................................................... 17
JTAG Interface ................................................................................................................................................... 17
Block Diagram ........................................................................................................................................................ 18
Block Diagram Description ..................................................................................................................................... 19
Data Processing/Flow ........................................................................................................................................ 19
10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) Block ................................................................ 22
SONET/SDH Mapping ....................................................................................................................................... 23
Mapper Block ..................................................................................................................................................... 23
Demapper Block ................................................................................................................................................ 25
Ethernet Ports .................................................................................................................................................... 27
Microprocessor Interface ................................................................................................................................... 27
SDRAM Memory Interface ................................................................................................................................. 27
Parallel Telecom Bus Interface .......................................................................................................................... 27
High and Low Order POH (Path Overhead Byte) Port Interface ....................................................................... 29
High and Low Order Alarm Indication Port Interface ......................................................................................... 29
Alarms and Performance Monitoring Blocks ...................................................................................................... 29
JTAG Interface ................................................................................................................................................... 29
Power-Up Sequencing ........................................................................................................................................... 29
Application Example ............................................................................................................................................... 30
Lead Diagram ......................................................................................................................................................... 31
Lead Descriptions ................................................................................................................................................... 32
Absolute Maximum Ratings and Environmental Limitations (Referenced to VSS) ................................................ 47
Thermal Characteristics ......................................................................................................................................... 47
Power Requirements .............................................................................................................................................. 48
Input, Output and Input/Output Parameters ........................................................................................................... 49
Timing Characteristics ............................................................................................................................................ 54
Operation ................................................................................................................................................................ 93
SONET/SDH Processing ................................................................................................................................... 93
General ......................................................................................................................................................... 93
Transmit High Order Path Termination (VC-3/VC-4/STS-1/STS-3C POH Generator) ...................................... 97
General ......................................................................................................................................................... 97
J1 .................................................................................................................................................................. 97
B3 .................................................................................................................................................................. 97
C2 .................................................................................................................................................................. 97
G1 ................................................................................................................................................................. 97
H4 .................................................................................................................................................................. 98
F2, F3/Z3, K3/Z4, and N1/Z5 ........................................................................................................................ 98
Receive High Order Path Termination (VC-3/VC-4/STS-1/STS-3C POH Monitor) ........................................... 98
General ......................................................................................................................................................... 98
J1 .................................................................................................................................................................. 98
B3 .................................................................................................................................................................. 99
C2 ................................................................................................................................................................ 100
G1 ............................................................................................................................................................... 100
H4 ................................................................................................................................................................ 100
F2, F3/Z3, K3/Z4, and N1/Z5 ...................................................................................................................... 100
High Order POH Port Interface ........................................................................................................................ 100
High Order Alarm Indication Port Interface ...................................................................................................... 101
AU-4 and AU-3 Pointer Generation ................................................................................................................. 102
Drop Bus Timing Mode ............................................................................................................................... 102
Add Bus Timing Mode 1 .............................................................................................................................. 102
Add Bus Timing Mode 2 .............................................................................................................................. 103
TU-3 Pointer Generation .................................................................................................................................. 103
TU-3 Pointer Tracking ...................................................................................................................................... 103
VC-3/STS-1/TUG-3 Timeslot Interchange ....................................................................................................... 103
VT/TU Pointer Tracking ................................................................................................................................... 103
VT/TU Pointer Generation ............................................................................................................................... 103
Low Order Timeslot Interchange ..................................................................................................................... 103
PRELIMINARY TXC-04236-MB, Ed. 3
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DATA SHEET
EtherMap-3 Plus
TXC-04236
TABLE OF CONTENTS (cont.)
Section
Page
Transmit Low Order Path Termination (Low Order POH Generator) ............................................................... 104
General ........................................................................................................................................................ 104
J2 ................................................................................................................................................................. 104
BIP-2 ............................................................................................................................................................ 104
Signal Label ................................................................................................................................................. 105
REI/RDI ....................................................................................................................................................... 105
K4/Z7 Bit 2 ................................................................................................................................................... 105
V5 RFI ......................................................................................................................................................... 105
N2/Z6 ........................................................................................................................................................... 105
Receive Low Order Path Termination (Low Order POH Monitor) .................................................................... 106
General ........................................................................................................................................................ 106
J2 ................................................................................................................................................................. 106
BIP-2 ............................................................................................................................................................ 106
Signal Label ................................................................................................................................................. 107
REI/RDI/RFI ................................................................................................................................................. 107
K4/Z7 Bit 2 ................................................................................................................................................... 107
N2/Z6 ........................................................................................................................................................... 107
Low Order and High Order Path Monitor Alarm Registers ............................................................................... 108
Low Order POH Port Interface ......................................................................................................................... 110
Low Order Alarm Indication Port Interface ....................................................................................................... 111
SONET/SDH Protection Switching Recovery Time .............................................................................................. 112
Virtual Concatenation and LCAS .......................................................................................................................... 113
Low Order Virtual Concatenation without LCAS .............................................................................................. 113
Low Order Virtual Concatenation with LCAS ................................................................................................... 115
High Order Virtual Concatenation without LCAS ............................................................................................. 116
High Order Virtual Concatenation with LCAS .................................................................................................. 119
Configuration for Virtual concatenation and LCAS ........................................................................................... 120
General ........................................................................................................................................................ 120
Configuring Transmit VCAT (Ethernet to SONET/SDH) .............................................................................. 121
Configuring Receive VCAT (SONET/SDH to Ethernet) ............................................................................... 122
LCAS-Specific Configuration - Transmit ...................................................................................................... 123
Assigning Unused VCGs (When at least one VCG is LCAS) .................................................................... 124
Dynamic Mapping and Virtual Concatenation Changes ................................................................................... 124
VCG Tributary Assignments (Adding and Removing Members) ................................................................. 124
Changing VCG Encapsulation/Decapsulation Mode ................................................................................... 126
Changing VCG SONET/SDH Structure ....................................................................................................... 126
Differential Delay Compensation ...................................................................................................................... 129
Maximum Differential Delay Allowed ........................................................................................................... 129
Maximum Differential Delay Detected ......................................................................................................... 130
Ethernet Support ................................................................................................................................................... 131
SMII and GMII Interfaces ................................................................................................................................. 131
Ethernet MAC Blocks ....................................................................................................................................... 133
Ethernet Frame Size .................................................................................................................................... 134
Ethernet Half Duplex ........................................................................................................................................ 134
Carrier Sense .............................................................................................................................................. 134
Collision Detection ....................................................................................................................................... 134
Alternate BEB Truncation ............................................................................................................................ 135
Excessive Collisions .................................................................................................................................... 135
Half-Duplex Flow Control ............................................................................................................................. 135
Flow Control Operation ......................................................................................................................................... 136
Overview .......................................................................................................................................................... 136
Full Duplex flow control .................................................................................................................................... 136
Definitions .................................................................................................................................................... 136
Flow Control Algorithm ................................................................................................................................ 136
TxFIFO Overflow ......................................................................................................................................... 136
External Pause Frames ............................................................................................................................... 136
Configuring Full Duplex Flow Control .......................................................................................................... 137
Changing Configurations ............................................................................................................................. 138
Encapsulation/Decapsulation ............................................................................................................................... 139
Setting the Encapsulation Mode ...................................................................................................................... 139
Changing the Encapsulation Mode .................................................................................................................. 140
GFP .................................................................................................................................................................. 141
GFP Host Insertion/Extraction of Management/Control Frames ...................................................................... 148
GFP Linear Frame Mode Operation ................................................................................................................. 150
Transmit Side Linear Extension Header ...................................................................................................... 150
Transmit Side CID Configuration Tables ..................................................................................................... 150
Receive Side Linear Extension Header ....................................................................................................... 152
Receive Side CID Configuration Tables ...................................................................................................... 152
LAPS ................................................................................................................................................................ 153
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TXC-04236
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TABLE OF CONTENTS (cont.)
Section
Page
LAPF ................................................................................................................................................................ 162
PPP (with BCP and LCP Support) ................................................................................................................... 170
SDRAM Controller ................................................................................................................................................ 183
SDRAM Memory Interface ............................................................................................................................... 183
CAS Latency ............................................................................................................................................... 183
BANK/ROW Activation ................................................................................................................................ 183
Commands .................................................................................................................................................. 184
Reset Configuration of SDRAM Controller ...................................................................................................... 184
Configuration Changes/Initialization ................................................................................................................ 184
Microprocessor Access to SDRAM .................................................................................................................. 185
Reset Operation ................................................................................................................................................... 186
General ............................................................................................................................................................ 186
External Lead Controlled Hardware Reset ...................................................................................................... 186
Microprocessor Controlled Hardware Reset .................................................................................................... 186
Microprocessor Controlled Soft Reset ............................................................................................................. 186
Microprocessor Controlled Global Performance Counter Reset ...................................................................... 186
Telecom Bus Operation ........................................................................................................................................ 187
General ............................................................................................................................................................ 187
Drop Bus Interface ........................................................................................................................................... 187
Drop Bus Parity Selection ................................................................................................................................ 187
Add Bus Interface ............................................................................................................................................ 188
Add Bus Timing Modes .................................................................................................................................... 188
Add Bus Parity Selection ................................................................................................................................. 189
Add Bus Delay ................................................................................................................................................. 190
Telecom Bus Tributary Activation/Tri-State Control ......................................................................................... 191
VC-3/VC-4 ................................................................................................................................................... 191
TUG-3 ......................................................................................................................................................... 191
TUG-2 ......................................................................................................................................................... 191
TU-11/TU-12 ............................................................................................................................................... 191
Loop Backs ........................................................................................................................................................... 193
MAC Loopback ................................................................................................................................................ 193
Telecom Bus Loopbacks ................................................................................................................................. 194
Boundary Scan ..................................................................................................................................................... 195
Introduction ...................................................................................................................................................... 195
Boundary Scan Operation ............................................................................................................................... 195
Boundary Scan Schematic .............................................................................................................................. 196
Boundary Scan Chain ...................................................................................................................................... 196
Memory Information ............................................................................................................................................. 197
General Device Registers ................................................................................................................................ 200
Table 10 through 12 - General Configuration and Status of the Device ..................................................... 200
Ethernet MAC Registers .................................................................................................................................. 201
Tables 13 through 17 - Status Information of the MAC ............................................................................... 201
Tables 18 through 23 - Configuration of the MAC ....................................................................................... 210
Tables 24 through 29 - MII Management Interface (used for MAC0 only) .................................................. 215
Ethernet MAC Registers .................................................................................................................................. 217
Tables 30 through 34 - Configuration, Alarms and Interrupts of the Ethernet MACs .................................. 217
Tx Encapsulation Registers ............................................................................................................................. 219
Tables 35 through 47 - Configuration, Status and Alarms of the Encapsulation Block ............................... 219
Rx Decapsulation Registers ............................................................................................................................ 236
Tables 48 through 61 - Configuration, Status and Alarms of the Decapsulation Block ............................... 236
SDRAM Control Registers ............................................................................................................................... 268
Table 62 - SDRAM Control and SDRAM Interface Configuration .............................................................. 268
Table 63 and 64 - Microprocessor Access to the SDRAM (Indirect Access) .............................................. 269
Tx Virtual Concatenation Registers ................................................................................................................. 270
Tables 65 through 75 - Configuration, Status and Alarms of the Transmit (Ethernet to SONET)
Virtual Concatenation Block ....................................................................................................................... 270
Rx Virtual Concatenation Registers ................................................................................................................. 283
Tables 76 through 85 - Configuration, Status and Alarm of the Receive
(SONET to Ethernet) Virtual Concatenation Block ...................................................................................... 283
Ethernet to SONET Handling Registers .......................................................................................................... 295
Tables 86 through 90 - Configuration and Status of the Ethernet Frame Format Block
(Output of the Ethernet MAC) ..................................................................................................................... 295
Table 91 through 103 - Ethernet Buffering and Flow Control in Transmit (Ethernet to SONET)
and Receive (SONET to Ethernet) Paths .................................................................................................... 296
Tx Mapper Block Registers .............................................................................................................................. 302
Tables 104 through 107 - Configuration, Status and Interrupt handling of the Transmit Mapper Block ...... 302
Tables 108 through 118 - Configuration of the Transmit Mapper Block ...................................................... 302
Rx DeMapper Block Registers ......................................................................................................................... 306
Tables 119 through 131 - Configuration, Status and Alarms for the Receive Demapper Block .................. 306
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EtherMap-3 Plus
TXC-04236
Section
TABLE OF CONTENTS (cont.)
Page
Tables 132 through 154 - Configuration, Status and Alarms of the Low Order POH Monitor ..................... 308
Tables 155 through 162 - Configuration, Status and Alarms of the Low Order
Tx Alarm Indication (RING) Port .................................................................................................................. 316
Table 163 - Configuration of the Low Order Rx Alarm Indication (RING) Port ............................................ 317
Tables 164 through 166 - Configuration and Status of the general Low Order Interrupt Controller ............ 318
Table 167 - Configuration of the High Order Rx Alarm Indication (RING) Port ........................................... 318
Tables 168 through 176 - Configuration, Status and Alarms of the High Order
Tx Alarm Indication (RING) Port .................................................................................................................. 318
Tables 177 through 209 - Configuration, Status and Alarms of the High Order POH Monitor .................... 320
Tables 210 through 222 - Configuration, Status and Alarms of the TU-3 PTR Tracker .............................. 332
Tables 223 and 224 - Configuration of TU-3 Cross Connect ...................................................................... 334
Tables 225 through 237 - Configuration, Status and Alarms of the TU-3 PTR Generator .......................... 335
Tables 238 through 242 - Configuration of High Order (VC-3 and VC-4) POH Generator .......................... 337
Tables 243 through 250 - Configuration, Status and Alarms of the TU-3 Retimer ...................................... 339
Tables 251 through 258 - Configuration, Status and Alarms of the AU-3/4 Retimer ................................... 341
Tables 259 through 261 - Configuration and Status of the General High Order Interrupt Controller .......... 342
Tables 262 through 280 - Configuration, Status and Alarms of the Rx Combus Interface .......................... 343
Tables 281 through 302 - Configuration, Status and Alarms of the Tx Combus Interface .......................... 347
Tables 303 through 305 - Configuration and Status of the General Combus Interface Interrupt Controller 350
Tables 306 through 308 - Configuration and Status of the General VTMAPPER Interrupt Controller ........ 351
Alarms, Performance and Fault Monitoring .......................................................................................................... 353
Terminology ..................................................................................................................................................... 353
System Alarm (Raw, Unlatched Alarm) ....................................................................................................... 353
Alarm Event ................................................................................................................................................. 353
Latched Alarm ............................................................................................................................................. 353
Secondary Alarm Inhibition .......................................................................................................................... 353
Interrupt Mask .............................................................................................................................................. 354
Performance and Fault Monitoring (PM and FM) ........................................................................................ 354
Performance Monitoring (PM) ..................................................................................................................... 354
Fault Monitoring (FM) .................................................................................................................................. 354
1-Second Clock ........................................................................................................................................... 354
Performance Counters ................................................................................................................................ 354
Unlatched Alarms ............................................................................................................................................. 355
Inhibition of Secondary Unlatched Alarm Generation .................................................................................. 355
Latched Alarms ................................................................................................................................................ 355
Latched Alarm Bits for Interrupt Generation (Lalarm_name/L1alarm_name) .................................................. 356
Latched Alarm Masking Bits (Malarm_name) .................................................................................................. 357
Secondary Latched Alarm Inhibition ................................................................................................................ 358
Latched Alarm Bits for PM/FM (L2ALARM_name), Performance Monitoring
(PM Bits; Palarm_name) and Fault Monitoring (FM Bits; Falarm_name) ........................................................ 359
Positive Edge Events ................................................................................................................................... 360
Negative Edge Events ................................................................................................................................. 361
Positive or Negative Edge Events ............................................................................................................... 362
Overall Alarm Generation and PM/FM Process Diagram ................................................................................ 363
Performance Counters ..................................................................................................................................... 364
Scheme A - Counters with Roll-Over/Saturation Option .............................................................................. 364
Scheme B - Performance Counters with 1-second Shadow Register Option ............................................. 364
Alarm Feature Combinations ........................................................................................................................... 365
System Alarm, Interrupt, and PM/FM Hierarchy .............................................................................................. 366
Alarm Interrupt Tree ......................................................................................................................................... 368
Register Tree ................................................................................................................................................... 376
Mapper/Demapper Performance Monitoring .................................................................................................... 378
Mapper/Demapper Interrupt Tree ................................................................................................................ 379
Mapper/Demapper PM/FM Tree per Block .................................................................................................. 383
Mapper/Demapper Consequent Actions per Block ..................................................................................... 390
Package Information ............................................................................................................................................. 394
Ordering Information ............................................................................................................................................. 395
Related Products .................................................................................................................................................. 395
Standards Documentation Sources ...................................................................................................................... 396
List of Data Sheet Changes .................................................................................................................................. 398
Please note that TranSwitch provides documentation for all of its products. Current editions of many documents are available
from the Products page of the TranSwitch Web site at www.transwitch.com. Customers who are using a TranSwitch Product,
or planning to do so, should register with the TranSwitch Marketing Department to receive relevant updated and
supplemental documentation as it is issued. They should also contact the Applications Engineering Department to ensure
that they are provided with the latest available information about the product, especially before undertaking development of
new designs incorporating the product.
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PRELIMINARY TXC-04236-MB, Ed. 3
July 2004