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T1Mx28 Device
DS1 Mapper 28-Channel
TXC-04228
DATA SHEET
FEATURES
• Twenty-eight independent 1.544 Mbit/s DS1
mappers
• Single/dual byte-parallel Telecom Bus @ 6.48
MHz (28 slots) or 19.44 MHz (84 slots)
• Floating VT1.5 byte-synchronous mapping with
signaling only for use with or without a slip buffer
• Asynchronous mapping for DS1
• SONET mapping (VT1.5) or SDH mapping
(VC-4/AU-3/TU-11)
• AMI or B8ZS codec for DS1s, or NRZ
• Serial I/O for control of DS1 line interface
transceivers or framers
• Telecom Bus and DS1 loopbacks with integral
PRBS generator and analyzer
• VT1.5/TU-11 pointer tracking and generation
• VT1.5/TU-11 overhead processing and insertion
• One-second latched performance registers and
counters
• DS1 alarm detection and generation
• Internal ring port for use as a dual bus
14-channel mapper
• Gapped line clock option for Internet applications
without need for a framer
• Intel/Motorola-compatible microprocessor
interface
• 3-bit RDI support
• Boundary scan capability (IEEE 1149.1)
• Single +3.3 V, ±5 % power supply
• 456-lead plastic ball grid array
package (35 x 35 mm)
DESCRIPTION
The T1Mx28is a 28-channel byte-synchronous and asyn-
chronous DS1 mapper. Four field-proven DS1MX7 DS1
Mapper chips are interconnected in a single compact pack-
age to permit higher application board densities. Both
SONET and SDH mappings are provided per Bellcore GR-
253-CORE (VT1.5) and ITU G.707 3-96. A single-dual add/
drop Telecom Bus is provided that can operate at either 6.48
or 19.44 MHz, which is compatible with other TranSwitch
devices. VT1.5/TU-11 pointer tracking and overhead extrac-
tion/processing with full error and alarm control is provided.
VT1.5/TU-11 pointer calculation and overhead assembly is
also provided. Alarm and error mappings from drop to add
and SONET/SDH to/from DS1 are provided. Jitter perfor-
mance is achieved with a fully digital threshold modulator
and DPLL that meets GR-253-CORE MTIE requirements
without external de-jitter buffers. For the DS1 line, AMI, B8ZS
and NRZ line codes are supported with full alarm detection
and generation per ANSI T1.231-1997. Each channel is
independently programmable for mixed service applications.
Access to status and control bits is provided via an Intel/
Motorola-compatible microprocessor interface. Diagnostic,
test, and maintenance functions are provided, including
boundary scan, PRBS generator/analyzer and loopbacks.
APPLICATIONS
• SONET/SDH terminal or add/drop multiplexers sup-
porting both asynchronous and byte-synchronous
modes
• Unidirectional or bidirectional ring applications
• SONET remote digital terminal equipment
• SONET CPE equipment requiring access to DS0s
• SONET/SDH test equipment
• Internet access equipment
SYSTEM SIDE
Line Transceiver Common
Control Interface
3 (x 4)
+3.3V
LINE SIDE
Add Bus
21
4 DS1 Dual Rail/
T1Mx28
NRZ Data &
u.comDrop Bus
Telecom Bus
Interface (x 2)
13
DS1 Mapper 28-Channel
TXC-04228
53
Clocks (x 28)
4
Line Transceiver
2 Alarm/Select Interface (x 28)
t4 Test Access Port Interface System
e for Boundary Scan
Clocks
heU.S. Patents No. 4,967,405; 5,033,064; 5,040,170;
s5,265,096; 5,289,507; 5,297,180; 5,528,598; 5,535,218
taU.S. and/or foreign patents issued or pending
Copyright 2001 TranSwitch Corporation
aT1Mx28 is a trademark of TranSwitch Corporation
.dTranSwitch and TXC are registered trademarks of TranSwitch Corporation
Microprocessor
Interface
Document Number:
PRELIMINARY TXC-04228-MB
Ed. 4, September 2001
w TranSwitch Corporation 3 Enterprise Drive Shelton, Connecticut 06484 USA
ww Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com

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T1Mx28
TXC-04228
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TABLE OF CONTENTS
Section
Page
List of Figures .................................................................................................................................... 3
Features ............................................................................................................................................ 4
Features that are Independently Selectable for each of the Mappers ....................................... 4
Features that are only Selectable for the Twenty-Eight Mappers as a Group ........................... 7
Block Diagram ................................................................................................................................... 9
Block Diagram Description .............................................................................................................. 10
Lead Diagram .................................................................................................................................. 15
Lead Descriptions ............................................................................................................................ 16
Absolute Maximum Ratings and Environmental Limitations ........................................................... 29
Thermal Characteristics .................................................................................................................. 29
Power Requirements ....................................................................................................................... 29
Input, Output and Input/Output Parameters .................................................................................... 30
Timing Characteristics ..................................................................................................................... 33
Operation ......................................................................................................................................... 49
General Mapper Application Overview ..................................................................................... 49
Line Interface Selection ............................................................................................................ 49
Asynchronous Operation with the Line Interface .............................................................. 50
Byte-Synchronous Operation with the Line Interface ........................................................ 52
Receive Data and Signaling Highway Operation .............................................................. 52
Transmit Data and Signaling Highway Operation ............................................................. 55
The Synchronizer, Mapper and Overhead Generator ....................................................... 57
Pointer Generation and Telecom Bus Slot Selection ........................................................ 59
VT/TU Pointer Tracking and Telecom Bus Slot Selection ................................................ 63
The Demapper .................................................................................................................. 66
Desynchronization and Pointer Leak Rate Calculations ................................................... 68
Jitter Measurements ................................................................................................................. 71
Microprocessor Interface and Common Control/Status I/O ..................................................... 77
Serial Port Control Interface ..................................................................................................... 81
T1Mx28 Channel Testing using the PRBS Generator and Analyzer ................................ 81
Telecom Bus Interface ............................................................................................................. 83
Multiplex Format and Mapping Information .............................................................................. 87
Internal Ring Port ..................................................................................................................... 93
Test Access Port ...................................................................................................................... 94
Boundary Scan Support .................................................................................................... 94
Device Reset Procedure .......................................................................................................... 96
Memory Map ................................................................................................................................... 97
Memory Map Descriptions ............................................................................................................. 102
Common Memory Map ........................................................................................................... 102
Per Channel Control Registers .............................................................................................. 118
Per Channel Status Registers ................................................................................................ 128
Application Diagrams .................................................................................................................... 141
Package Information ..................................................................................................................... 142
Ordering Information ..................................................................................................................... 143
Related Products ........................................................................................................................... 143
Standards Documentation Sources ............................................................................................... 144
List of Data Sheet Changes .......................................................................................................... 146
Documentation Update Registration Form* .............................................................................. 149
* Please note that TranSwitch provides documentation for all of its products. Current editions of many
documents are available from the Products page of the TranSwitch Web site at www.transwitch.com.
Customers who are using a TranSwitch Product, or planning to do so, should register with the
TranSwitch Marketing Department to receive relevant updated and supplemental documentation as it
is issued. They should also contact the Applications Engineering Department to ensure that they are
provided with the latest available information about the product, especially before undertaking devel-
opment of new designs incorporating the product.
PRELIMINARY TXC-04228-MB
Ed. 4, September 2001
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DATA SHEET
T1Mx28
TXC-04228
LIST OF FIGURES
Figure
Page
1 T1Mx28 TXC-04228 Block Diagram ....................................................................................... 9
2 VT1.5/TU-11 Asynchronous and Byte-Synchronous Mappings ............................................ 13
3 T1Mx28 TXC-04228 Lead Diagram ...................................................................................... 15
4 Tributary Input Timing ........................................................................................................... 33
5 Tributary Output Timing ........................................................................................................ 34
6 Signaling Highway Structure ................................................................................................. 35
7 Serial Control Port Structure and Timing .............................................................................. 36
8 Telecom Bus Input Timing - 6.48 MHz Operation ................................................................. 37
9 Telecom Bus Input Timing - 19.44 MHz Operation ............................................................... 38
10 Telecom Bus Output Timing - 6.48 MHz Operation .............................................................. 39
11 Telecom Bus Output Timing - 19.44 MHz Operation ............................................................ 40
12 Datacom Mode Output Timing .............................................................................................. 42
13 Datacom Mode Input Timing ................................................................................................. 43
14 Intel Microprocessor Read Cycle Timing .............................................................................. 44
15 Motorola Microprocessor Read Cycle Timing ....................................................................... 45
16 Intel Microprocessor Write Cycle Timing ............................................................................... 46
17 Motorola Microprocessor Write Cycle Timing ....................................................................... 47
18 Boundary Scan Timing .......................................................................................................... 48
19 Line Interface for Dual Unipolar Mode .................................................................................. 51
20 Line Interface for NRZ Mode ................................................................................................. 51
21 Byte-Synchronous Interface to a DS1 Framer ...................................................................... 52
22 System Interface Receive Framing Format ........................................................................... 54
23 System Interface Receive Signaling Format ......................................................................... 54
24 System Interface Transmit Framing Format .......................................................................... 56
25 System Interface Transmit Signaling Format ........................................................................ 56
26 VT/TU Pointer Tracking State Machine ................................................................................. 65
27 Pointer Leak Rate Algorithm ................................................................................................. 70
28 Jitter Tolerance Test Setup ................................................................................................... 71
29 Jitter Tolerance Measurements ............................................................................................. 72
30 Jitter Transfer Test Setup ...................................................................................................... 73
31 Jitter Transfer Measurements ............................................................................................... 73
32 Jitter Generation Test Setup ................................................................................................. 74
33 Standard Pointer Test Sequences ........................................................................................ 76
34 Shadow Register Operation .................................................................................................. 80
35 Serial Interface Operation ..................................................................................................... 81
36 Loopbacks and Built-in PRBS Testing of the T1Mx28 .......................................................... 82
37 Telecom Bus Structure; SONET or VC-3 SDH; Telecom Bus @ 6.48 MHz ......................... 85
38 Telecom Bus Structure; TUG-3 SDH; Telecom Bus @ 19.44 MHz ...................................... 86
39 STS-1 SPE Mapping ............................................................................................................. 87
40 STS-3/AU-3 Mapping ............................................................................................................ 89
41 STM-1/VC-4 Mapping ........................................................................................................... 91
42 Internal Ring Port Operation ................................................................................................. 93
43 Boundary Scan Schematic .................................................................................................... 95
44 Typical Applications using the T1Mx28 ............................................................................... 141
45 T1Mx28 TXC-04228 456-Lead Plastic Ball Grid Array Package ......................................... 142
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T1Mx28
TXC-04228
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
FEATURES
The following features are supported by the T1Mx28:
The T1Mx28 device is a highly-featured twenty-eight-channel DS1 (T1) mapper for use in a wide variety of
interface, transmission and switching applications. Twenty-eight independent DS1 asynchronous/byte-synchro-
nous mappers are provided in a VLSI device using sub-micron CMOS technology. Powered from a single +3.3
volt supply, the device dissipates less than two watts typically. The T1Mx28 is provided in a 456-lead plastic
ball grid array package (35 x 35 mm). Its ambient operating temperature range extends from -40 °C to 85 °C
with 0 ft/min airflow.
The T1Mx28 device has been designed to meet the latest industry standards, namely:
ANSI T1.102- 1993
ANSI T1.105- 1991
ANSI T1.107- 1995
ANSI T1.231 1997
ANSI T1.403-1998
AT&T Pub. 62411 (December 1990)
Bellcore GR-253-CORE (Issue 2)
Bellcore TR-NWT-000496 (Issue 3)
Bellcore GR-499-CORE (Issue 1)
IEEE 1149.1- 1990, -1994
ITU -T G.707 3-96
ITU -T G.783
FEATURES THAT ARE INDEPENDENTLY SELECTABLE FOR EACH OF THE MAPPERS
Line Interface Options
Meets ANSI and Bellcore input jitter requirements
Rail (for asynchronous mapping only)
B8ZS or AMI
ANSI compliant LOS detector
ANSI compliant AIS detector
12-bit BPV counters with excessive zeros option
NRZ option (for asynchronous and byte-synchronous mapping)
Clock polarity selection for clock in/out
NRZ data inversion and clock edge options (separate transmit and receive control)
For asynchronous use, negative rail can be used to count externally detected code violations
Programmable clock edges for transmit and receive data
External lead per channel for status (may be programmed to combine with internal AIS and
LOS to support external LOC detector)
Clock slave for asynchronous input; clock and multiframe synchronization (3 ms), master or
slave, for byte-synchronous input
Separate signaling highway for byte-synchronous, carries ABCD signaling bits and AIS/
Yellow alarm information in and out of the T1Mx28 (see TXC-03108, 8-Channel T1 Framer)
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DATA SHEET
T1Mx28
TXC-04228
External lead-controlled shut down of all DS1 per A or B Telecom Bus line drive leads for
card protection
Gapped clock option in place of signaling for 1536 kHz datacom in byte-synchronous
operation
CRC-6 generation (DS1 input) and error counting (DS1 output) in byte-synchronous mapping
Mapping and Synchronizer Features
Mapping to SONET or SDH columns according to GR-253-CORE or ITU G.709
Per channel selectable asynchronous and byte-synchronous mapping to a floating
VT1.5 or TU-11 for both mapping and demapping
Overhead assembly with BIP-2 calculation, REI-FEBE (microprocessor or received BIP-2
error), signal label (microprocessor value), RDI (microprocessor value or via received signal
label mismatch, VT AIS, VT LOP, or unequipped) and RFI (microprocessor value or DS1
Yellow from signaling highway)
Pointer calculation (fixed at 78 for asynchronous, calculated for byte-synchronous mode) with
generated pointer increment and decrement counters (4 bits each)
In byte-synchronous mode, line clock may be an input (modified byte-synchronous mode) or
an output (true byte-synchronous mode)
Multiplexing of signaling bits from the signaling highway with P0/P1 bit generation
Unequipped and unassigned VT payload generation
VT AIS generation (microprocessor value, AIS from signaling highway, loss of frame on byte-
synchronous, or AIS/LOS/external lead from line decoder)
Threshold modulator to reduce demapping jitter and wander
Tracking of input multiframe pulses by pointer movements in byte-synchronous mode
Demapping and Desynchronizer Features
Asynchronous or byte-synchronous per channel, programmable to match mapper mode
Digital PLL with 2 Hz low pass filter to track up to ± 250 Hz nominal DS1 signal providing a
smooth clock output with no need for an external de-jitter buffer
Separate ± 5 byte pointer leak buffer with programmable dual slope leak rate
(8 ms to 2048 ms per bit in 8 ms steps, automatically doubled to 16 ms to 4096 ms per bit in
16 ms steps within ± 12 bits of center of pointer leak buffer); meets Bellcore MTIE with
minimal software support
Power down with all-zeros or all-ones sent to line interface
Demapping of SONET or SDH columns according to GR-253-CORE or ITU G.709
Asynchronous and byte-synchronous demapping of a floating VT1.5/TU-11
Pointer tracking and extraction of overhead (V5 and Z7/K4), LOP, AIS, SS and NDF with
received pointer increment and decrement counters (4 bits each)
Overhead processing with BIP-2 calculation and error counting (12-bit, with overflow), REI
(FEBE) counting (12-bit, with overflow), RDI (1- and 3-bit)/RFI signal label debouncing and
detection, signal label mismatch/unequipped detection
Demultiplexing of signaling bits to the signaling highway with multiframe generation for byte-
synchronous
DS1 AIS from microprocessor value, VT AIS, VT LOP, signal label mismatch or unequipped
DS1 RAI (Yellow) to signaling highway from RFI
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