MK1493-02A.pdf 데이터시트 (총 24 페이지) - 파일 다운로드 MK1493-02A 데이타시트 다운로드

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MK1493-02A
Networking/PCI Clock Generator
Description
The MK1493-02A is a general purpose clock generator
that provides an integrated clocking solution for
PCI/Networking applications. It provides two pairs of
differential CPU clocks, four PCI clocks, seven PCI_X
clocks, two reference clocks, additional clock selectable
from REF/50 MHz, and six pairs of SSTL2 DDR at
2.5 V. All complementary outputs operate only from
a 2.5 V power supply.
Input/Output Features
Packaged in 56-pin TSSOP package
2 - Pairs of differential CPU clocks (differential
current mode)
4 - PCI @ 3.3 V
7 - PCI_X @ 3.3 V
2 - REF @ 3.3 V, Fixed
6 - Pairs of differential SSTL2 DDR @ 2.5 V
1 - REF/50 MHz, selectable
Spread spectrum for EMI control
Supports SMBUS index read/write and blocks
read/write operations
Uses external 25 or 50 MHz crystal or clock
CPU output jitter <125 ps
PCI cycle to cycle output jitter <250 ps
DDR cycle to cycle output jitter <150 ps
Block Diagram
PLL2
50MHz/REF2
X1
External capacitor
required with crystal for
accurate timing of clock
XTAL
OSC
2 REF(0:1)
X2
PLL1
Spread
Spectrum
ww OE
w FREQSEL
FS (3:0)
.D SDATA
SCLK
a CLK_STOPB
ta PCI_STOPB
S SSEN
4
Control
Logic
Config.
Reg.
CPU
Divider
PCI
Divider
Stop
Stop
Delay
Delay
AGP
Divider
DDR
Divider
Stop
Stop
Delay
Delay
2
2
CPUCLKT (1:0)
CPUCLKC (1:0)
7 PCI_XCLK (6:0)
4 PCI (3:0)
6
6
DDRT (5:0)
DDRC (5:0)
IREF
heet4UMDS 1493-02A C
1
Revision 020204
.comIntegrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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Pin Assignment
VDDAND
X1
X2
REF2_50M
VDDREF
VSSREF
FREQSEL_REF0
REF1
SCL
SDA
PCI_XSTPB
CLKSTPB
PCI0
PCI1
PCI2
PCI3
VDDPCI
VSSPCI
VSSPCI_X2
VDDPCI_X2
FS0_PCI_X0
FS1_PCI-X1
FS2_PCI_X2
FS3_PCI_X3
SSEN_PCI_X4
PCI_X5
PCI_X6
VSSPCI_X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VSSAND
55 IREF
54 OE
53 CPUT0
52 CPUC0
51 VSSCPU
50 VDDCPU
49 CPUT1
48 CPUC1
47 VSSDR0
46 VDDDR0
45 DDRT0
44 DDRC0
43 DDRT1
42 DDRC1
41 VSSDR1
40 VDDDR1
39 DDRT2
38 DDRC2
37 DDRT3
36 DDRC3
35 VDDDR2
34 VSSDR2
33 DDRT4
32 DDRC4
31 DDRT5
30 DDRC5
29 VDDPCI_X1
56 pin 240mil 0.50 mm pitch TSSOP
Functionality Table
FIN
MHz
FS3
FS2
FS1
FS0
CPUCLK
MHz
50 0 1 0 0
50 0 1 0 1
25 0 1 1 0
25 0 1 1 1
251 1 0 0 0
25 1 0 0 1
25 1 0 1 0
25 1 0 1 1
25 1 1 0 0
25 1 1 0 1
25 1 1 1 0
25 1 1 1 1
1 Default start Output Clock settings,
33
100
33
33
1001
200
133
133
133
150
125
166
33M=33.33 MHz, 66M=66.66 MHz, 133M=133.33 MHz.
DDR
MHz
33
133
33
33
2001
200
133
133
133
150
125
166
MK1493-02A
Networking/PCI Clock Generator
PCI
MHz
33
33
33
33
661
66
33
33
66
33
33
33
PCI_X
MHz
33
33
33
133
331
33
66
33
66
33
33
33
MDS 1493-02A C
2
Revision 020204
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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MK1493-02A
Networking/PCI Clock Generator
Pin Descriptions
Pin Pin Pin
Name
Type
Pin Description
1
VDDAND
Power Analog and digital power supply 3.3 V.
2
X1/CLK
XI Crystal connection/input clock. Connect to a 25 MHz fundamental mode crystal.
3 X2 XO Connect to a 25 MHz fundamental mode crystal or leave unconnected if X1 is a
4
REF2_50M
Output REF2 or 50 MHz output.
5
VDDREF
Power Power supply for REF outputs.
6
VSSREF
Power Ground for REF outputs.
7 FREQSEL_REF0 I/O Input frequency select input pin for 50 MHz/ REF2 (0=50 MHz select, 1=REF2
select). Output - REF0.( Internal Pull up resistor of 120K ohms see for page 21)
8
REF1
Output REF1 clock output.
9 SCL I/O Clock pin for SMBUS circuitry. 5 V tolerant.
10
SDA
Input Data pin for SMBUS circuitry. 5 V tolerant.
11
PCI_XSTPB
Input Asynchronous input Stops all PCI_XCLK at logic level 0 when pulled low.( Internal
pull up resistor 120K)
12
CUP_STPB
Input Asynchronous input halts CPU , DDR and PCI clocks at logic O when driven low. S.
(Internal pull up resistor 120K see page 21)
13
PCI0
Output PCI Output clock 0.
14
PCI1
Output PCI Output clock 1.
15
PCI2
Output PCI Output clock 2.
16
PCI3
Input PCI Output clock 3.
17
VDDPCI1
Power Power supply for PCI clocks.
18
VSSPCI1
Power Ground supply for PCI clocks.
19
VSSPCI_X2
Power Ground for PCI_X clocks.
20
VDDPCI_X2
Power Power supply for PCI_X clocks.
21
FS0_PCI_X0
I/O FS0 input/PCI_X0 output. (Internal Pull Down resistor 120K , see page 21).
22
FS1_PCI-X1
I/O FS1 input/PCI_X1 output. (Internal Pull Down resistor 120K , see page 21)
23
FS2_PCI_X2
I/O FS2 input/PCI_X2 output. (Internal Pull Down resistor 120K , see page 21).
24
FS3_PCI_X3
I/O FS3 input/PCI_X3 output. (Internal Pull up resistor 120K , see page 21).
25
SSEN_PCI4
I/O Spread spectrum enable (0=SS disabled, 1=enabled). PCI clock output. (Internal pull
down resistor 120K see page 21)
26
PCI_X5
Output PCI_X clock output.
27
PCI_X6
Output PCI_X clock output.
28
VSSPCI_X1
Power Ground for PCI clocks.
29
VDDPCI_X1
Power Power supply for PCI clocks.
30
DDRC5
Output Complementary clock output of DDRT5.
31
DDRT5
Output True clock output of DDRT5.
32
DDRC4
Output Complementary clock output of DDRT4.
33
DDRT4
Output True clock output of DDRT4.
34
VSSDR2
Power Ground for DDR clocks.
35
VDDDR2
Power Power supply for DDR clocks (2.5 V only for complementary outputs).
36
DDRC3
Output Complementary clock output of DDRT3.
MDS 1493-02A C
3
Revision 020204
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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MK1493-02A
Networking/PCI Clock Generator
Pin Pin Pin
Name
Type
Pin Description
37
DDRT3
Output True clock output of DDRT3.
38
DDRC2
Output Complementary clock output of DDRT2.
39
DDRT2
Output True clock output of DDRT2.
40
VDDDR1
Power Power supply for DDR clocks 2.5 V only for complementary outputs.
(Can use 3.3 V supply for single ended outputs)
41
VSSDR1
Power Ground for DDR clocks.
42
DDRC1
Output Complementary clock output of DDRT1.
43
DDRT1
Output True clock output of DDRT1.
44
DDRC0
Output Complementary clock output of DDRT0.
45
DDRT0
Output True clock output of DDRT0.
46
VDDDR0
Power Power supply for DDR clocks 2.5 V only for complementary outputs).
(Can use 3.3 V supply for single ended outputs)
47
VSSDR0
Power Ground for DDR clocks.
48
CPUC1
Output Complementary CPU clock output.
49
CPUT1
Output True CPU clock output.
50
VDDCPU
Power Power supply for CPU Clocks 3.3 V.
51
VSSCPU
Power Ground for CPU clocks.
52
CPUC0
Output Complementary CPU clock output.
53
CPUT0
Output True CPU clock output.
54 OE Input Enables all outputs when high, tri-state outputs when low. Pull-up.
55
IREF
Output A precision resistor connected to ground establishes the external reference current.
56
VSSAND
Power Analog and digital ground power supply.
MDS 1493-02A C
4
Revision 020204
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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MK1493-02A
Networking/PCI Clock Generator
General SMBUS Serial Interface Info
General SM-Bus Serial Interface
Information
How to Write:
Controller (host) sends a start bit
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the beginning byte location =
N
ICS clock will acknowledge
Controller sends Byte Count X
ICS clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
T starT
Slave
Address D2
WR
(H)
ACK
Beg Location = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
O
O
O
ACK
O
O
O
Byte N + X - 1
ACK
P stoP
How to Read:
Controller (host) will send a start bit
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the beginning Byte location =
N
ICS clock will acknowledge
Controller (host) will send a repeat start bit
Controller (host) sends the read address Byte D3 (H)
ICS clock will acknowledge
ICS clock will send the data Byte count = X
ICS clock sends Byte N
ICS clock sends Byte N+X-1
Controller (host) will need to acknowledge each Byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T
Slave Address
D2 (H)
starT bit
WR
=0
ACK
Beginning Loc = N
ACK
RT repeat
starT
Slave Address
D2 (H)
RD
=1
ACK
Data Byte Count=X
ACK
ACK
O
O
O
Beginning Byte N
X
B
Y
O
TO
EO
S
Byte N + X - 1
N NAK
P stoP bit
MDS 1493-02A C
5
Revision 020204
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com