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Preliminary Technical Data
16-Bit, 80/100 MSPS, A/D Converter
AD9446
FEATURES
100 MSPS guaranteed sampling rate
100 dB two-tone SFDR with 30 MHz and 31 MHz
81.6 dB SNR with 30 MHz input (3.2 V p-p input, 80Msps)
90 dBc SFDR with30 MHz input (3.2 V p-p input, 80Msps)
Excellent linearity
DNL = ±0.5 LSB typical
INL = ±3.0 LSB typical
2.3 W power dissipation
3.3 V and 5 V supply operation
2.0 V p-p to 3.2 V p-p differential full-scale input
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos compliment)
Output clock available
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9446 is a 16-bit monolithic, sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for power, small size, and ease of use. The product
w operates at up to a 100 MSPS conversion rate and is optimized
for multicarrier, multimode receivers, such as those found in
w cellular infrastructure equipment.
wThe ADC requires 3.3 V and 5.0 V power supplies and a low
.Dvoltage differential input clock for full performance operation.
No external reference or driver components are required for
amany applications. Data outputs are LVDS-compatible (ANSI-
t644) or CMOS-compatible and include the means to reduce
athe overall current needed for short trace distances.
Sheet4Rev. PrF
UInformation furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
.infringements of patents or other rights of third parties that may result from its use.
cSpecifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
omregistered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
VIN+
VIN-
CLK+
CLK-
AGND AVDD1 AVDD2 DRGND DRVDD
AD9446
BUFFER
T/H
CLOCK
&TIMING
MANAGEMENT
PIPELINE
ADC
REF
CMOS
16 OR LVDS
OUTPUT
STAGING
2
32
2
DFS
DCS MODE
OUTPUT
MODE
OR
D15-
D0
DCO
VREF SENSE REFT REFB
Figure 1.
Optional features allow users to implement various selectable
operating conditions, including data format select and output
data mode.
The AD9446 is available in a 100-lead surface-mount plastic
package (100-lead TQFP/EP) specified over the industrial
temperature range −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. True 16 bit linearity.
2. High performance: outstanding SFDR performance for multi-
carrier, multimode 3G and 4G cellular base station receivers.
3. Ease of use: on-chip reference and track-and-hold. An
output clock simplifies data capture.
4. Packaged in a Pb-free, 100-lead TQFP/EP.
5. Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
6. OR (out-of-range) outputs indicate when the signal is beyond
the selected input range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

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AD9446
TABLE OF CONTENTS
DC Specifications ............................................................................. 3
AC Specifications.............................................................................. 4
Digital Specifications........................................................................ 6
Switching Specifications .................................................................. 7
Explanation of Test Levels ........................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Definitions of Specifications ......................................................... 10
Pin Configurations and Function Descriptions ......................... 11
Equivalent Circuits ......................................................................... 16
REVISION HISTORY
5/05—PrF: Preliminary Version
Preliminary Technical Data
Typical Performance Characteristics ........................................... 17
Theory of Operation ...................................................................... 18
Analog Input and Reference Overview ................................... 18
Clock Input Considerations...................................................... 20
Power Considerations................................................................ 21
Digital Outputs ........................................................................... 21
Timing ......................................................................................... 21
Operational Mode Selection ..................................................... 21
Evaluation Board ........................................................................ 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
Rev. PrF | Page 2 of 24

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Preliminary Technical Data
AD9446
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.2 V p-p differential input, internal
trimmed reference (1.6 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error
VOLTAGE REFERENCE
Output Voltage1 (VREF = 1.6 V)
(VREF = 1.0 V)
Load Regulation @ 1.0 mA
Reference Input Current
(External 1.6 V Reference)
INPUT REFERRED NOISE
ANALOG INPUT
Input Span (VREF = 1.6 V)
(VREF = 1.0 V)
Input Common-Mode Voltage
Input Resistance3
Input Capacitance3
POWER SUPPLIES
Supply Voltage
AVDD1
AVDD2
DRVDD—LVDS Outputs
DRVDD—CMOS Outputs
Supply Current
AVDD1
AVDD22
IDRVDD2—LVDS Outputs
IDRVDD2—CMOS Outputs
PSRR
Offset
Gain
POWER CONSUMPTION
DC Input—LVDS Outputs
DC Input—CMOS Outputs
Temp
Full
Test
Level
VI
AD9446BSVZ-80
Min Typ
Max
AD9446BSVZ-100
Min Typ
Max
16
Unit
Bits
Full VI
Full VI
Full VI
Full VI
25°C I
Full VI
Guaranteed
±0.3
±0.5
±3.0
Guaranteed
±0.3
±0.5
±3.0
1.5
mV
% FSR
LSB
LSB
LSB
Full V
Full V
μV/°C
%FS/°C
Full VI
Full VI
Full V
Full VI
25°C V
1.6
1.0
±2
2.50
1.6 V
1.0 V
±2 mV
μA
2.75 LSB rms
Full V
Full V
Full V
Full V
Full V
3.2
2.0
3.5
1
2.5
3.2 V p-p
2.0 V p-p
3.5 V
1 kΩ
2.5 pF
Full IV
Full IV
Full IV
Full IV
Full VI
Full VI
Full VI
Full V
Full V
Full V
Full VI
Full V
3.14 3.3
4.75 5.0
3.0
3.0 3.3
338
209
65
14
1
0.2
2.3
2.1
3.46 3.14 3.3
5.25 4.75 5.0
3.6 3.0
3.6 3.0 3.3
366
220
65
14
1
0.2
2.5
2.3
3.46 V
5.25 V
3.6 V
3.6 V
mA
mA
mA
mA
mV/V
%/V
W
W
1 The internal voltage reference is trimmed at final test to minimize the gain error of the AD9446.
2 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
3 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input
structure.
Rev. PrF | Page 3 of 24

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AD9446
Preliminary Technical Data
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.2 V p-p differential input, internal
trimmed reference (1.6 V mode), AIN = −1 dBFS, DCS on, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10 MHz
fIN = 10 MHz (2 V p-p Input)
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
SIGNAL-TO-NOISE AND DISTORTION
fIN = 10 MHz
fIN = 10 MHz (2 V p-p Input)
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 10 MHz
fIN = 10 MHz (2 V p-p)
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
WORST HARMONIC, SECOND OR THIRD
fIN = 10 MHz
fIN = 10 MHz (2 V p-p)
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
Test AD9446BSVZ-80
Temp Level Min Typ Max
25°C IV
Full IV
25°C IV
Full IV
25°C I
Full IV
25°C IV
Full IV
25°C V
81.9
77.5
81.6
80.3
78.5
25°C IV
Full IV
25°C IV
Full IV
25°C I
Full IV
25°C IV
Full IV
25°C V
80.9
77.3
80.7
78.7
78.0
25°C V
25°C V
25°C V
25°C V
13.2
13.1
13.1
12.7
25°C IV
Full IV
25°C IV
Full IV
25°C I
Full IV
25°C IV
Full IV
25°C V
90
90
90
83
82
25°C IV
Full IV
25°C IV
Full IV
25°C I
Full IV
25°C IV
Full IV
25°C V
−90
−90
−90
−83
−82
AD9446BSVZ-100
Min Typ Max
79.6
76
79.5
79.0
78.6
78.9
75.5
78.5
77.2
76.6
13.0
12.9
12.7
12.6
90
90
88
84
82
−90
−90
−89
−84
−82
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Rev. PrF | Page 4 of 24

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Preliminary Technical Data
Parameter
WORST SPUR EXCLUDING SECOND
OR THIRD HARMONICS
fIN = 10 MHz
fIN = 10 MHz (2 V p-p)
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
TWO-TONE SFDR
fIN = 10.8 MHz @ −7 dBFS,
9.8 MHz @ −7 dBFS
fIN = 70.3 MHz @ −7 dBFS,
69.3 MHz @ −7 dBFS
ANALOG BANDWIDTH
AD9446
Test AD9446BSVZ-80
Temp Level Min Typ Max
AD9446BSVZ-100
Min Typ Max
Unit
25°C IV
Full IV
25°C IV
Full IV
25°C I
Full IV
25°C IV
Full IV
25°C V
25°C V
25°C V
Full V
−95
−95
−90
−90
−85
95
325
−96 dBc
dBc
−95 dBc
dBc
−95 dBc
dBc
−95 dBc
dBc
−94 dBc
95 dBFS
dBFS
540 MHz
Rev. PrF | Page 5 of 24