Preliminary Technical Data
16-Bit, 80/100 MSPS, A/D Converter
100 MSPS guaranteed sampling rate
100 dB two-tone SFDR with 30 MHz and 31 MHz
81.6 dB SNR with 30 MHz input (3.2 V p-p input, 80Msps)
90 dBc SFDR with30 MHz input (3.2 V p-p input, 80Msps)
DNL = ±0.5 LSB typical
INL = ±3.0 LSB typical
2.3 W power dissipation
3.3 V and 5 V supply operation
2.0 V p-p to 3.2 V p-p differential full-scale input
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos compliment)
Output clock available
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
The AD9446 is a 16-bit monolithic, sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for power, small size, and ease of use. The product
w operates at up to a 100 MSPS conversion rate and is optimized
for multicarrier, multimode receivers, such as those found in
w cellular infrastructure equipment.
wThe ADC requires 3.3 V and 5.0 V power supplies and a low
.Dvoltage differential input clock for full performance operation.
No external reference or driver components are required for
amany applications. Data outputs are LVDS-compatible (ANSI-
t644) or CMOS-compatible and include the means to reduce
athe overall current needed for short trace distances.
UInformation furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
.infringements of patents or other rights of third parties that may result from its use.
cSpecifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
omregistered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2 DRGND DRVDD
16 OR LVDS
VREF SENSE REFT REFB
Optional features allow users to implement various selectable
operating conditions, including data format select and output
The AD9446 is available in a 100-lead surface-mount plastic
package (100-lead TQFP/EP) specified over the industrial
temperature range −40°C to +85°C.
1. True 16 bit linearity.
2. High performance: outstanding SFDR performance for multi-
carrier, multimode 3G and 4G cellular base station receivers.
3. Ease of use: on-chip reference and track-and-hold. An
output clock simplifies data capture.
4. Packaged in a Pb-free, 100-lead TQFP/EP.
5. Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
6. OR (out-of-range) outputs indicate when the signal is beyond
the selected input range.
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Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.