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6116A: 11/8/89
Revision: Monday, November 8, 1993
www.DataSheet4U.com
Features
D Adeusteolmecatteidc powerĆdown when
D CMOS for optimum speed/power
D
High speed
Ċ 20 ns
D Low active power
Ċ 550 mW
D LĊow11s0tamnWdby power
D TTLĆcompatible inputs and outputs
D Cthaapna2b0le01oVf weiltehcstrtaonstdaitnicgdgirsecahtaerrge
CCYY66111167AA
2K x 8 Static RAM
Functional Description
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WtI(h/WOeriEtpci)nihngiisnpt(poIeu/tOnhtsae0badtlreheevriob(cCuoegtEihhsa)ILc/OaOcnoW7dm).ipwsDlwirsairhtteiaettdoeewnnnhaitnbehtlneoe
tdhreesms peminosr(yAlo0ctahtriooungshpAec1if0i)e.d on the adĆ
Ri(mcopnOonieangnEaitstnhcd.e)hseinnLiHtapgsOdItoeGdhWnfreHetahdsbw.seelUhevpmiinilc(needeCsmewiEwsrorati)irhltcyleacealonsoepemdcnpcaapeootbaliuniolrstednhpoie(utnsiWdptotebnheEcyseni,tf)aItaib/herkOldeeĆeĆ
wTsthraiteteeIwe/Onhaebpnlienchs(iWrpeEemn)aaiibnslLeinO(CWhEi.gh)ĆiismHpeIGdaHncoer
TcohaetCtoYi6n1su16reAaalpnhdaCiYm6m1u1n7Aityu. tilize a die
Logic Block Diagram
A10
A9
A8
A7
A6
A5
A4
CE
WE
OE
INPUT BUFFER
128 x 16 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
A3
A2
A1 A0
Pin Configurations
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
6116A-1
DToIpP/VSiOewJ
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1 24
2 23
3 22
4 21
5 20
6 19
6116A
7 18
8 17
9 16
10
11
12
15
14
13
VCC
A8
A9
WE
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
ToLpCVCiew
A3
A2
NC
NC
A1
A0
I/O0
4 3 2 1 28 27 26
5 25
6 24
7 23
8
6116A
22
9 21
10
20
11
19
1213 14 151617 18
WE
OE
A10
NC
NC
CE
I/O7
6116A-2
ToLpCVCiew
6116A-3
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
4 3 2 1 32 31 30
5
6
7
8
9
10
11
12
13
6117A
29
28
27
26
25
24
23
22
21
14 15 16 17 1819 20
A8
A9
NC
WE
OE
A10
CE
I/O7
I/O6
6116A-4
Selection Guide
Maximum Access Time (ns)
MCuarxriemnut m(mOAp)erating
MCuarxriemnut m(mSAta)ndby
Commercial
Military
Commercial
Military
66111167AA--2200
20
100
40/20
66111167AA--2255
25
100
125
20
40
66111167AA--3355
35
100
100
20
20
66111167AA--4455
45
100
100
20
20
66111167AA--5555
55
80
100
20
20
Cypress Semiconductor Corporation D 3901 North First St1reet D San Jose FebDruaryC1A989851-34ReviDsed D40e8ce-m9b4e3r-12969020

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6116A: 11/8/89
Revision: Monday, November 8, 1993
CY6116A
CY6117A
Mwwawx.iDmatuamSheReat4tUin.cgoms
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature . . . . . . . . . . . . . . . . . . -65 _C to +150_C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . . . . . . . -55 _C to +125_C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . -3.0V to +7.0V
Output Current into Outputs (LOW) . . . . . . . . . . . . . . 20 mA
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . >2001V
(per MILĆSTDĆ883, Method 3015)
LatchĆUp Current . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Operating Range
Range
Commercial
Military [1]
Ambient
Temperature
0_C to +70_C
-55_C to +125_C
VCC
5V ± 10%
5V ± 10%
Electrical Characteristics Over the Operating Range [2]
6116A-20
6117A-20
6116A-25, 35, 45
6117A-25, 35, 45
6116A-55
6117A-55
Parameter
VOH
VOL
VIH
VIL
IIX
IOZ
IOS
ICC
ISB1
ISB2
Description
Test Conditions
Min. Max.
Output HIGHVoltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage [3]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current [4]
VCC Operating
Supply Current
Automatic CE
PowerĆDown Current
- TTL Inputs
VCC = Min., IOH = -4.0 mA
VCC = Min., IOL = 8.0 mA
GND < VI < VCC
GND < VI < VCC,
Output Disabled
VCC = Max., VOUT = GND
VCC = Max.
IOUT = 0 mA
f = fMAX = 1/tRC
Max. VCC,
CE > VIH
f = fMAX
Com'l
Mil 25
35, 45
Com'l
Mil 25
35, 45, 55
2.4
2.2
-0.5
-10
-10
0.4
VCC
0.8
+10
+10
-300
100
40
Automatic CE
PowerĆDown Current
- CMOS Inppuuttss
Max. VCC,
CE > VIH - 0.3V,
VIN > VCC - 0.3V
or VIN < 0.3V,
f=0
Com'l
Mil
20
Min.
2.4
2.2
-0.5
-10
-10
Max.
0.4
VCC
0.8
+10
+10
Min. Max.
2.4
2.2
-0.5
-10
-10
0.4
VCC
0.8
+10
+10
Unit
V
V
V
V
mA
mA
-300
-300 mA
100 80 mA
125 100
100
20 20 mA
40 20
20
20 20 mA
20 20
Capacitance [5]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25_C, f = 1 MHz,
VCC = 5.0V
Max.
10
10
Unit
pF
pF
Notes:
1. TA is the instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing inĆ
formation.
3. VIL (min.) = -3.0V for pulse durations less than 30 ns.
4. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect
these parameters.
2

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6R1e1v6isAio:n1:1M/8o/8n9day, November 8, 1993
CY6116A
CY6117A
AwCwwT.DesattaLShoeaedt4sUa.cnodm Waveforms
5V
OUTPUT
R1 481W
5V
OUTPUT
30 pF
INCJLSIUGCDAOINNPGDE
R2525W
(a)
5 pF
INCJLSIUGCDAOINNPGDE
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167W 1.73V
R1 481W
R2525W
(b) 6116A-5
3.0V
GND 10%
5 ns
ALL INPUT PULSES
90%
90%
10%
5 ns
6116A-6
Switching Characteristics Over the Operating Range [2, 6]
6116A-20
6117A-20
6116A-25
6117A-25
6116A-35
6117A-35
6116A-45
6117A-45
6116A-55
6117A-55
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
20 25 35 45 55
ns
tAA
Address to Data Valid
20 25 35 45 55 ns
tOHA
Data Hold from Address Change
5
5
5
5
5
ns
tACE
CE LOW to Data Valid
20 25 35 45 55 ns
tDOE
OE LOW to Data Valid
10 12 15 20 25 ns
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z [7]
CE LOW to Low Z [8]
CE HIGH to High Z [7, 8 ]
3 3 3 3 3 ns
8 10 12 15 20 ns
5 5 5 5 5 ns
8 10 15 15 20 ns
tPU
CE LOW to PowerĆUp
0 0 0 0 0 ns
tPD CE HIGH to PowerĆDown
WRITE CYCLE [9]
20 20 20 25 25 ns
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Write Cycle Time
CE LOW to Write End
Address SetĆUp to Write End
Address Hold from Write End
Address SetĆUp to Write Start
WE Pulse Width
Data SetĆUp to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
20 20 25 40 50
ns
15 20 25 30 40
ns
15 20 25 30 40
ns
0 0 0 0 0 ns
0 0 0 0 0 ns
15 15 20 20 25
ns
10 10 15 15 25
ns
0 0 0 0 0 ns
7 7 10 15 20 ns
5 5 5 5 5 ns
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing refĆ
erence levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified I OL/IOH and 30ĆpF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with C L = 5 pF as in part (b)
of AC Test Loads. Transition is measured ±500 mV from steady state
voltage.
8. At any given temperature and voltage condition, t HZCE is less than
tLZCE for any given device.
9. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setĆ
up and hold timing should be referenced to the rising edge of the signal
that terminates the write.
3