INA8583N contains 256х8 RAM 8-bit. The word address register which is incremented automati-
cally, built-in 32.768 kHz oscillator circuit, frequency divider, interface of two line bi-directional
serial I2C-bus and power-on reset circuit.
The first 8 bits of the RAM (addresses 00÷07) are designated ass addressable 8-bit parallel
registers. The first register (address 00) is used as a control/status register. The memory addresses
01 to 07 are used as counters for the clock function. The memory address 08÷0F may be used as
free RAM locations or may be programmed as alarm registers.
The following modes can be selected by setting the control/status register:
Clock mode from 32.768 kHz;
Clock mode from 50 Hz;
Event counter mode.
In the clock mode hundredths of a second, seconds, minutes, hours, date, month (four-year
calendar) and a weekday are stored in a BCD format. The timer register stores up to 99 days. The
event counter mode is used for counting pulses applied to the oscillator input (OSCO left open-
circuit). In BCD format the event counter stores up to 6 digits.
By setting the alarm enabling bit of the control/status register the alarm control register (ad-
dress 08) is activated.
By setting the alarm control register the following may be programmed:
In the clock mode the timer register (address 07) may be programmed to count hundredths
of a second, seconds, minutes, hours or days. Days are counted when an alarm is not programmed.
Whenever an alarm event occurs the alarm flag of the control/status register is set, and an
overflow condition of the timer will set the timer flag. The open drain interrupt output is switched
on (active LOW) when the alarm or timer flag is set. The flags remain set until directly reset by a
write operation to register (00 address).
When the alarm is disabled the remaining alarm registers (addresses 09÷0F) may be used as
In the clock modes 24hr or 12hr format can be selected by setting the most significant bit of
the hours counter register.