DP8440.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 DP8440 데이타시트 다운로드

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February 1995
DP8440-40 DP8440-25 DP8441-40 DP8441-25
microCMOS Programmable 16 64 Mbit
Dynamic RAM Controller Driver
General Description
The DP8440 41 Dynamic RAM Controllers provide an easy
interface between dynamic RAM arrays and 8- 16- 32- and
64-bit microprocessors The DP8440 41 DRAM Controllers
generate all necessary control and timing signals to suc-
cessfully interface and design dynamic memory systems
With significant enhancements over the DP8420 21 22
predecessors the DP8440 41 are suitable for high perform-
ance memory systems These controllers support page and
burst accesses for fast page static column and nibble
DRAMs Refreshes and accesses are arbitrated on chip
RAS low time during refresh and RAS precharge time are
guaranteed by these controllers Separate precharge coun-
ters for each RAS output avoid delayed back to back ac-
cesses due to precharge when using memory interleaving
Programmable features make the DP8440 41 DRAM Con-
trollers flexible enough to fit many memory systems
Features
Y 40 MHz and 25 MHz operation
Y Page detection
Y Automatic CPU burst accesses
Y Support 1 4 16 64 Mbits DRAMs
Y High capacitance drivers for RAS CAS WE and Q out-
puts
Y Support for fast page static column and nibble mode
DRAMs
Y High precision PLL based delay line
Y Byte enable for word size up to 32 bits on the DP8440
or 64 bits on the DP8441
Y Automatic Internal Refresh
Y Staggered RAS-Only refresh
Y Burst and CAS-before-RAS refresh
Y Error scrubbing during refresh
Y TRI-STATE outputs
Y Easy interface to all major microprocessors
Block Diagram
FIGURE 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11718
TL F 11718 – 1
RRD-B30M75 Printed in U S A

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DRAM
Controller
DP8440V-40
DP8440VLJ-40
DP8440VLJ-25
DP8441VLJ-40
DP8441VLJ-25
Maximum Clock
Frequency
40 MHz
40 MHz
25 MHz
40 MHz
25 MHz
Package
Type
84-Pin PLCC
100-Pin PQFP
100-Pin PQFP
100-Pin PQFP
100-Pin PQFP
Bus Width
Supporting
8 16 32
8 16 32
8 16 32
8 16 32 64
8 16 32 64
Largest DRAM
Possible
16 Mbits
16 Mbits
16 Mbits
64 Mbits
64 Mbits
1 0 CONNECTION DIAGRAMS
2 0 FUNCTIONAL INTRODUCTION
3 0 SIGNAL DESCRIPTION
3 1 Address and Control Signals
3 2 DRAM Control Signals
3 3 Refresh Signals
3 4 Reset and Programming Signals
3 5 Clock Inputs
3 6 Power Signals and Capacitor Input
4 0 PROGRAMMING AND RESETTING
4 1 Reset
4 2 Programming Sequence
4 3 Programming Selection Bits
5 0 ACCESS MODES
5 1 Opening Access
5 2 Normal Mode
5 3 Page Mode
5 4 Burst Access
5 5 Inner Page Burst Access
6 0 REFRESH MODES
6 1 Auto-Internal Refresh
6 2 Externally Controlled Refresh
6 3 Error Scrubbing during Refresh
6 4 Extending Refresh
6 5 Refresh Types
Table of Contents
7 0 WAIT SUPPORT
7 1 DTACK During Opening Access
7 2 DTACK During Page Access
7 3 DTACK During Burst Access
7 4 Next Address or Early DTACK Support
8 0 ABSOLUTE MAXIMUM RATINGS
9 0 DC ELECTRICAL CHARACTERISTICS
10 0 LOAD CAPACITANCE
11 0 AC TIMING PARAMETERS
12 0 AC TIMING WAVEFORMS
CLK and DECLK Timing
Refresh Timing
Refresh and Access Timing
Programming and Initialization Period Timing
Normal Mode Access Timing
Page Mode Access Timing
Burst Mode Access Timing
13 0 ERRATA
14 0 PHYSICAL DIMENSIONS
2

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1 0 Connection Diagrams
Top View
FIGURE 2
Order Number DP8441VLJ-40 (40 MHz Operation) DP8441VLJ-25 (25 MHz Operation)
See NS Package Number VLJ100A
TL F 11718 – 2
3

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1 0 Connection Diagrams (Continued)
Top View
FIGURE 3
Order Number DP8440VLJ-40 (40 MHz Operation) DP8440VLJ-25 (25 MHz Operation)
See NS Package Number VLJ100A
TL F 11718 – 38
4

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1 0 Connection Diagrams (Continued)
Top View
FIGURE 4
Order Number DP8440V-40 (40 MHz Operation)
See NS Package Number V84A
TL F 11718 – 3
5