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July 1993
DP8430V 31V 32V-33 microCMOS Programmable
256k 1M 4M Dynamic RAM Controller Drivers
General Description
The DP8430V 31V 32V dynamic RAM controllers provide a
low cost single chip interface between dynamic RAM and
all 8- 16- and 32-bit systems The DP8430V 31V 32V gen-
erate all the required access control signal timing for
DRAMs An on-chip refresh request clock is used to auto-
matically refresh the DRAM array Refreshes and accesses
are arbitrated on chip If necessary a WAIT or DTACK out-
put inserts wait states into system access cycles including
burst mode accesses RAS low time during refreshes and
RAS precharge time after refreshes and back to back ac-
cesses are guaranteed through the insertion of wait states
Separate on-chip precharge counters for each RAS output
can be used for memory interleaving to avoid delayed back
to back accesses because of precharge An additional fea-
ture of the DP8432V is two access ports to simplify dual
accessing Arbitration among these ports and refresh is
done on chip
Features
Y On chip high precision delay line to guarantee critical
DRAM access timing parameters
Y microCMOS process for low power
Y High capacitance drivers for RAS CAS WE and DRAM
address on chip
Y On chip support for nibble page and static column
DRAMs
Y Byte enable signals on chip allow byte writing in a word
size up to 32 bits with no external logic
Y Can use a single clock source Up to 33 MHz operating
frequency
Y On board Port A Port B (DP8432V only) refresh arbitra-
tion logic
Y Direct interface to all major microprocessors
Y 4 RAS and 4 CAS drivers (the RAS and CAS configura-
tion is programmable)
Control
DP8430V
DP8431V
DP8432V
of Pins
(PLCC)
68
68
84
of Address
Outputs
9
10
11
Largest
DRAM
Possible
256 kbit
1 Mbit
4 Mbit
Direct Drive
Memory
Capacity
4 Mbytes
16 Mbytes
64 Mbytes
Access
Ports
Available
Single Access Port
Single Access Port
Dual Access Ports (A and B)
Block Diagram
DP8430V 31V 32V DRAM Controller
TRI-STATE is a registered trademark of National Semiconductor Corporation
Staggered RefreshTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11118
FIGURE 1
TL F 11118 – 1
RRD-B30M75 Printed in U S A

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Table of Contents
1 0 INTRODUCTION
2 0 SIGNAL DESCRIPTIONS
2 1 Address R W and Programming Signals
2 2 DRAM Control Signals
2 3 Refresh Signals
2 4 Port A Access Signals
2 5 Port B Access Signals (DP8432V)
2 6 Common Dual Port Signals (DP8432V)
2 7 Power Signals and Capacitor Input
2 8 Clock Inputs
5 2 Refresh Cycle Types
5 2 1 Conventional Refresh
5 2 2 Staggered RefreshTM
5 2 3 Error Scrubbing Refresh
5 3 Extending Refresh
6 0 PORT A WAIT STATE SUPPORT
6 1 WAIT Type Output
6 2 DTACK Type Output
6 3 Dynamically Increasing the Number of Wait States
6 4 Guaranteeing RAS Low Time and RAS Precharge
Time
3 0 PROGRAMMING AND RESETTING
3 1 Reset
3 2 Programming Methods
3 2 1 Mode Load Only Programming
3 2 2 Chip Selected Access Programming
3 3 Internal Programming Modes
7 0 RAS AND CAS CONFIGURATION MODES
7 1 Byte Writing
7 2 Memory Interleaving
7 3 Address Pipelining
7 4 Error Scrubbing
7 5 Page Burst Mode
4 0 PORT A ACCESS MODES
4 1 Access Mode 0
4 2 Access Mode 1
4 3 Extending CAS with Either Access Mode
4 4 Read-Modify-Write Cycles with Either Access Mode
4 5 Additional Access Support Features
4 5 1 Address Latches and Column Increment
4 5 2 Address Pipelining
4 5 3 Delay CAS During Write Accesses
8 0 TEST MODE
9 0 DRAM CRITICAL TIMING PARAMETERS
9 1 Programmable Values of tRAH and tASC
9 2 Calculation of tRAH and tASC
10 0 DUAL ACCESSING (DP8432V)
10 1 Port B Access Mode
10 2 Port B Wait State Support
10 3 Common Port A and Port B Dual Port Functions
5 0 REFRESH OPTIONS
5 1 Refresh Control Modes
5 1 1 Automatic Internal Refresh
5 1 2 Externally Controlled Refresh
10 3 1 GRANTB Output
10 3 2 LOCK Input
11 0 ABSOLUTE MAXIMUM RATINGS
12 0 DC ELECTRICAL CHARACTERISTICS
13 0 AC TIMING PARAMETERS
14 0 DP8430V 31V 32V USER HINTS
2

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1 0 Introduction
The DP8430V 31V 32V DRAM controllers are the latest
devices based upon the DP8420A 21A 22A predecessors
The DP8430V 31V 32V implement changes which do not
allow them to be pin compatible with any of the DP842XA or
the DP842XV DRAM controllers Two changes have been
made The limits for the input frequency to DELCLK have
been increased making possible the use of a single clock
source A RESET input is now available making the reset
procedure easier These changes although minimal facili-
tate the use of the controllers and make them even more
attractive for high performance applications The controllers
incorporate address latches refresh counter row column
refresh address multiplexer delay line refresh access pre-
charge arbitration logic and high capacitive drivers The
DP8430V 31V 32V DRAM controllers allow any manufac-
turer’s CPU or bus to directly interface to DRAM arrays up to
64 Mbytes in size
Reset
The user must reset the controller before programming it
Reset is achieved by asserting the RESET input for at least
16 positive edges of clock
Programming
After reset the user can program the controller by either
one of two methods Mode Load Only Programming or Chip
Select Access Programming The chip is programmed
through the address bus
Initialization Period
Once the DP8430V 31V 32V has been programmed for the
first time a 60 ms initialization period is entered During this
time the DRC performs refreshes to the DRAM array so
further warm up cycles are unnecessary The initialization
period is entered only after the first programming after a
reset
Accessing Modes
After resetting and programming the chip the DP8430V
31V 32V is ready to access the DRAM There are two
modes of accessing with these controllers Mode 0 which
indicates RAS synchronously and Mode 1 which indicates
RAS asynchronously
Refresh Modes
Two refresh modes can be programmed The user can
choose Automatic Internal Refresh or Externally Controlled
Refresh With any refresh mode the user can perform burst
refreshes
Refresh Types
There are three types of refreshing available Conventional
Staggered and Error Scrubbing Any refresh control mode
can be used with any type of refresh
Wait Support
The DP8430V 31V 32V have wait support available as
DTACK or WAIT Both are programmable DTACK Data
Transfer ACKnowledge is useful for processors whose wait
signal is active high WAIT is useful for those processors
whose wait signal is active low The user can choose either
at programming These signals are used by the on chip arbi-
ter to insert wait states to guarantee the arbitration between
accesses refreshes and precharge Both signals are inde-
pendent of the access mode chosen and both signals can
be dynamically delayed further through the WAITIN signal to
the DP8430V 31V 32V
Sequential Accesses (Static Column Page Mode)
The DP8430V 31V 32V have address latches used to
latch the bank row and column address inputs Once the
address is latched a COLumn INCrement (COLINC) feature
can be used to increment the column address The address
latches can also be programmed to be fall through COLINC
can be used for Sequential Accesses of Static Column
DRAMs Also COLINC in conjunction with ECAS inputs can
be used for Sequential Accesses to Page Mode DRAMs
RAS and CAS Configuration (Byte Writing)
The RAS and CAS drivers can be configured to drive a one
two or four bank memory array up to 32 bits in width The
ECAS signals can then be used to select one of four CAS
drivers for Byte Writing with no extra logic
Memory Interleaving
When configuring the DP8430V 31V 32V for more than
one bank Memory Interleaving can be used By tying the
low order address bits to the bank select lines B0 and B1
sequential back to back accesses will not be delayed since
these controllers have separate precharge counters per
bank
Address Pipelining
The DP8430V 31V 32V are capable of performing Address
Pipelining In address pipelining the DRC will guarantee the
column address hold time and switch the internal multiple-
xor to place the row address on the address bus At this
time another memory access to another bank can be initiat-
ed
Dual Accessing
Finally the DP8432V has all the features previously men-
tioned and unlike the DP8430V 31V the DP8432V has a
second port to allow a second CPU to access the same
memory array The DP8432V has four signals to support
Dual Accessing these signals are AREQB ATACKB LOCK
and GRANTB All arbitration for the two ports and refresh is
done on chip by the controller through the insertion of wait
states Since the DP8432V has only one input address bus
the address lines must be multiplexed externally The signal
GRANTB can be used for this purpose
Terminology
The following explains the terminology used in this data
sheet The terms negated and asserted are used Asserted
refers to a ‘‘true’’ signal Thus ‘‘ECAS0 asserted’’ means
the ECAS0 input is at a logic 0 The term ‘‘COLINC assert-
ed’’ means the COLINC input is at a logic 1 The term negat-
ed refers to a ‘‘false’’ signal Thus ‘‘ECAS0 negated’’
means the ECAS0 input is at a logic 1 The term ‘‘COLINC
negated’’ means the input COLINC is at a logic 0 The table
shown below clarifies this terminology
Signal
Active High
Active High
Active Low
Active Low
Action
Asserted
Negated
Asserted
Negated
Logic Level
High
Low
Low
High
3

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Connection Diagrams
Top View
FIGURE 2
TL F 11118–2
Order Number DP8430V-33
See NS Package Number V68A
Top View
FIGURE 3
TL F 11118 – 3
Order Number DP8431V-33
See NS Package Number V68A
Top View
FIGURE 4
Order Number DP8432V-33
See NS Package Number V84A
4
TL F 11118 – 4

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2 0 Signal Descriptions
Pin
Name
Device (If not Input
Applicable to All) Output
Description
2 1 ADDRESS R W AND PROGRAMMING SIGNALS
R0 – 10
R0 – 9
DP8432V
DP8430V 31V
I ROW ADDRESS These inputs are used to specify the row address during an access
I to the DRAM They are also used to program the chip when ML is asserted (except
R10)
C0 – 10
C0 – 9
DP8432V
DP8430V 31V
I COLUMN ADDRESS These inputs are used to specify the column address during an
I access to the DRAM They are also used to program the chip when ML is asserted
(except C10)
B0 B1
I BANK SELECT Depending on programming these inputs are used to select a group
of RAS and CAS outputs to assert during an access They are also used to program
the chip when ML is asserted
ECAS0 – 3
I ENABLE CAS These inputs are used to enable a single or group of CAS outputs
when asserted In combination with the B0 B1 and the programming bits these
inputs select which CAS output or CAS outputs will assert during an access The
ECAS signals can also be used to toggle a group of CAS outputs for page nibble
mode accesses They also can be used for byte write operations If ECAS0 is
negated during programming continuing to assert the ECAS0 while negating AREQ
or AREQB during an access will cause the CAS outputs to be extended while the
RAS outputs are negated (the ECASn inputs have no effect during scrubbing
refreshes)
RESET
I RESET At power up this input is used to reset the DRAM controller The user must
keep RESET low for at least 16 positive edges of clock After programming this input
must remain negated (high) to avoid an unwanted reset
WIN
I WRITE ENABLE IN This input is used to signify a write operation to the DRAM If
ECAS0 is asserted during programming the WE output will follow this input This
input asserted will also cause CAS to delay to the next positive clock edge if address
bit C9 is asserted during programming
COLINC
(EXTNDRF)
I COLUMN INCREMENT When the address latches are used and RFIP is negated
I this input functions as COLINC Asserting this signal causes the column address to
be incremented by one When RFIP is asserted this signal is used to extend the
refresh cycle by any number of periods of CLK until it is negated
ML I MODE LOAD This input signal when low enables the internal programming register
that stores the programming information
2 2 DRAM CONTROL SIGNALS
Q0 – 10
Q0 – 9
Q0 – 8
DP8432V
DP8431V
DP8430V
O DRAM ADDRESS These outputs are the multiplexed output of the R0 – 9 10 and
O C0–9 10 and form the DRAM address bus These outputs contain the refresh
O address whenever RFIP is asserted They contain high capacitive drivers with 20X
series damping resistors
RAS0 – 3
O ROW ADDRESS STROBES These outputs are asserted to latch the row address
contained on the outputs Q0 – 8 9 10 into the DRAM When RFIP is asserted the
RAS outputs are used to latch the refresh row address contained on the Q0 – 8 9 10
outputs in the DRAM These outputs contain high capacitive drivers with 20X series
damping resistors
CAS0 – 3
O COLUMN ADDRESS STROBES These outputs are asserted to latch the column
address contained on the outputs Q0 – 8 9 10 into the DRAM These outputs have
high capacitive drivers with 20X series damping resistors
WE
(RFRQ)
O WRITE ENABLE or REFRESH REQUEST This output asserted specifies a write
O operation to the DRAM When negated this output specifies a read operation to the
DRAM When the DP8430V 31V 32V is programmed in address pipelining mode or
when ECAS0 is negated during programming this output will function as RFRQ
RFRQ asserted specifies that 13 ms or 15 ms have passed RFRQ can be used to
externally request a refresh through the input RFSH This output has a high
capacitive driver and a 20X series damping resistor
5