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m TECHNICAL DATA
et4U.co INF8574GENERAL DESCRIPTION
heThe INF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most
Smicrocontroller families via the two-line bidirectional bus (I2C).
taThe device consists of an 8-bit quasi-bidirectional Port and an I2C interface. The INF8574 has a low current
aconsumption and includes latched outputs with high current drive capability for directly driving LEDs. It
.Dalso possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller.
wBy sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming
wdata on its ports without having to communicate via the I2C-bus. This means that the INF8574 can remain a
w simple slave device.
FEATURES
m  Operating supply voltage 2.5 to 6 V
o  Low standby current consumption of 10  A maximum
  I2C to parallel port expander
.c  Open-drain interrupt output
  8-bit remote I/O Port for the I2C-bus
  Compatible with most microcontrollers
U  Latched outputs with high current drive capability for
t4directly driving LEDs
  Address by 3 hardware address pins for use of up to 8
edevices (up to 16 with INF8574A)
  DIP16, space-saving SO16 or SSOP20 package.
www.DataSheBLOCK DIAGRAM
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INF8574
PINNING
SYMBOL
A0
A1
A2
P0
P1
P2
P3
VSS
P4
P5
P6
P7
INT
SCL
SDA
VDD
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DESCRIPTION
address input 0
address input 1
address input 2
quasi-bidirectional I/O Port 0
quasi-bidirectional I/O Port 1
quasi-bidirectional I/O Port 2
quasi-bidirectional I/O Port 3
supply ground
quasi-bidirectional I/O Port 4
quasi-bidirectional I/O Port 5
quasi-bidirectional I/O Port 6
quasi-bidirectional I/O Port 7
interrupt output (active LOW)
serial clock line
serial data line
supply voltage
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is
not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals
Bit transfer.
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data
line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data
line while the clock is HIGH is defined as the stop condition (P).
Definition of start and stop conditions.
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INF8574
System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
System configuration.
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is
not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH
level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse,
set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to
enable the master to generate a stop condition.
Acknowledgement on the I2C-bus.
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FUNCTIONAL DESCRIPTION
INF8574
Simplified schematic diagram of each Port.
Addressing
For addressing.
INF8574
INF8574A
Slave addresses.
Each bit of the INF8574 I/O Port can be independently used as an input or output. Input data is transferred
from the Port to the microcontroller by the READ mode (see Fig.11). Output data is transmitted to the Port
by the WRITE mode (see Fig.10).
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INF8574
WRITE mode (output Port).
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