AV2388.pdf 데이터시트 (총 20 페이지) - 파일 다운로드 AV2388 데이타시트 다운로드

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AVS Tech.ncoomlogy AV2388
t4U Multi-Channel Audio CODEC
SheeFEATURES
ta• Six Channel 24/20-bit DACs.
.Da- 102 dB SNR
w- 104 dB Dynamic Range.
w - -92 dB THD + N Ratio.
w - 32,44.1, 48, 96 and 192KHz. Sampling
mrates.
- 24, 20, 18 and 16-bit Digital Inputs.
o- Containing Digital De-emphasis Filters.
.c- Independent Digital Volume Control.
- I2S, Left and Right Justified Digital Input
UFormats.
t4- Auto-Mute Control.
- On -chip Reconstruction Filters.
e- -96 dB THD + N Ratio.
e- I2S and Left Justified Output Formats.
• System clock: 384 fs or 256 fs for 32, 44.1
48, 96 and 192KHz. Sampling Rates, 192
fs or 128 fs for 96 KHz Sampling Rates.
and 86 fs or 64 fs for 192 KHz. Sampling
Rate.
• Automatic input format detection.
• 5-volt Power Supply.
• 3.3 -volt Digital Interface Friendly.
• I2C Interface for Mode Setting.
Applications
• Digital Surround Sound For Home Theater
• DVD
• Car Audio.
• 28 pin SOP package
taShSDA
aSCL
.DSD1
SD2
wSD3
80
80
77
I2C Serial
Control Port
AV2388
ww mSF 77
eet4U.coSC 78
Format
Detect'n
PLL
ataShXCK
w.DAVS Technology Inc.
w4110 Clipper Ct., Fremont CA94538
wTel: (510) 353-0848
1-20
15
RST
D/A 40KHz
D/A 40KHz
D/A 40KHz
D/A 40KHz
D/A 40KHz
D/A 40KHz
VOR3
VOL3
VOR2
VOL2
VOR1
VOL1
15
VCM
January 3, 2002
Fax: (510) 353-0856

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AV2388
Item
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PERFORMANCE SPECIFICATIONS
Audio DAC
Audio Output Level
Audio Bandwidth 20Hz - 20 KHz
SNR (A-weight, Muted)
SNR (A-weight, Not Muted)
THD + N (A-weight, FFS Output)
Dynamic Range
Channel Separation
Nonlinear Distortion
Channel Gain Error
Spec.
1 Vrms
+/- 0.1 dB
>102 dB
>96 dB
< -92 dB
104 dB
< -96 dB
< 0.25 dB
< 0.1 dB
All Measurement were taken with only one channel active.
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January 3, 2002

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AV2388
DESCRIPTION
The AV2388 is a mixed signal CMOS monolithic audio CODEC. It consists of six channels sigma delta DACs The
DACs support 24, 20, 18 and 16-bit input data. It also support multiple sampling frequency data. Each DAC has it
own individual volume control.
XCK REQUIREMENT
The AV2388 supports 384 and 256 times sampling clock for 32, 44.1, 48, 96 and 192K audio; 192 or 128 times for
the 96 K audio.; and 96 and 64 times for the 192K audio.
XCK Requirement
Sampling
Rate
PLLcntl=[0 0]
XCK Freq.
PLLcntl=[1 0]
PLLcntl=[0 1]
Normal XCK
4 times XCK
2 times XCK
384*fs
256*fs
4*384*fs
4*256*fs
2*384*fs
2*256*fs
32 K 12.288 MHz 8.192 MHz 49.152 MHz 32.768 MHz 24.576 MHz 16.384 MHz
44.1 16.934 Mhz 11.29 Mhz. 67.738 Mhz 45.158 Mhz. 33.869 Mhz 22.579 Mhz.
48 K 18.432 MHz 12.288 Mhz. 73.728 MHz 49.152 Mhz. 36.864 MHz 24.576 Mhz.
96 K 18.432 MHz 12.288 Mhz. 73.728 MHz 49.152 Mhz. 36.864 MHz 24.576 Mhz.
192 K 18.432 Mhz 12.288 Mhz. 73.728 Mhz 49.152 Mhz. 36.864 Mhz 24.576 Mhz.
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January 3, 2002

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PIN ASSIGNMENT
SD3
SD2
SD1
TSTO
SC
SF
DGND
DVDD
DGND
XCK
SCL
SDA
TST
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AV2388
28 AR1
27 AL1
26 AR2
25 AL2
24 AR3
23 AL3
22 AGND
21 VCM
20 AVDD
19 N/C
18 AGND
17 N/C
16 N/C
15 N/C
PIN DESCRIPTION
Pin Name
DIGITAL
SD3
SD2
SD1
TSTO
SC
SF
DGND
DVDD
DGND
XCK
Pin #
1
2
3
4
5
6
7
8
9
10
Type
Description
I Audio Serial Data Input 3.
I Audio Serial Data Input 2.
I Audio Serial Data Input 1,..
O Test output pin. This pin should be no be connected.
I Audio Serial Data Clock pin.
I Left/Right Channel Clock pin. For Left justified or Right justified mode, a high in
SF indicates Left Channel Data, a low in SF indicates Right Channel Data. For
I2S mode, a low in SF indicates Left Channel Data, a high in SF indicates Right
Channel Data.
GND Digital ground
+5V Digital power supply.
GND Digital ground
I External Master Clock Input.
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January 3, 2002

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AV2388
PIN DESCRIPTION (Continued)
Pin Name
SCL
SDA
TST
RST
Analog
AR1
AL1
AR2
AL2
AR3
AL3
AVSS
VCM
AVDD
N/C
AGND
N/C
N/C
N/C
Pin #
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Type
Description
I I2C clock input.
I/O I2C DATA bus. Open drain output. Externally this pin should tie to a 680 ohm
pull up resistor.
O Test fs reference pin. For test vector verification. For normal operation this pin
must be tied to ‘0’.
I Active low power down reset. When low, the chip is reset and all programmable
registers are reset to default values.
O Analog right channel 1 output
O Analog left channel 1 output
O Analog right channel 2 output.
O Analog left channel 2 output.
O Analog right channel 1 output.
O Analog left channel 1 output.
GND Analog circuits ground
Common voltage output pin for the DAC.
+5V Analog circuits power supply
No connection. Can be tied to AVSS
GND Analog circuits ground
I No connection. Can be tied to AVSS
I No connection. Can be tied to AVSS
No connection, Can be tied to AVSS
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January 3, 2002