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Preliminary
HT95L100/10P
8-Bit LCD Type Phone Controller MCU
Features
· Provide MASK type and OTP type version
· Operating voltage range: 2.4V~5.5V
· Program ROM: 4K´16 bits
· Data RAM: 1152´8 bits
· Up to 20 bidirectional I/O lines
· 16-bit table read instructions
· Eight-level subroutine nesting
· Timer:
- Two 16-bit programmable Timer/Event Counter
- Real time clock (RTC)
- Watchdog Timer (WDT)
· Programmable frequency divider (PFD)
· Dual system clock: 32768Hz, 3.58MHz
· Four operating modes: Idle mode, Sleep mode,
Green mode and Normal mode
· Up to 1.117ms instruction cycle with 3.58MHz system
clock
· Built-in 3.58MHz DTMF Generator
· LCD driver:
- 20 seg.´8 com.
- 4 segments can per nibble option to bidirectional
I/O lines
- LCD contrast can be adjusted by software or exter-
nal resistor
- Fixed frame frequency 64Hz
· Built-in Low Battery detector
· All instructions in one or two machine cycles
· Built-in dialer I/O
· 64-pin QFP package
Applications
· Deluxe Feature Phone
· Caller ID Phone
· Cordless Phone
· Fax and answering machines
· Other communication system
General Description
The HT95L100/10P are 8-bit high performance
RISC-like microcontrollers with built-in DTMF generator
and dialer I/O which provide MCU dialer implementation
or system control features for telecom product applica-
tion. The phone controller has a built-in program ROM,
data RAM, LCD driver and a maximum of 20 I/O lines for
high end products design. In addition, for power man-
agement purpose, it has a built-in frequency up conver-
sion circuit (32768Hz to 3.58MHz) which provides dual
system clock and four types of operation modes. For ex-
ample it can operate with low speed system clock rate of
32768Hz in green mode with little power consumption. It
can also operate with high speed system clock rate of
3.58MHz in normal mode for high performance opera-
tion. To ensure smooth dialer function and to avoid MCU
shut-down in extreme low voltage situation, the dialer
I/O circuit is built-in to generate hardware dialer signals
such as on-hook, hold-line and hand-free. Built-in real
time clock and programmable frequency divider are pro-
vided for additional fancy features in product develop-
ments. The device is best suitable for feature phone
products that comply with versatile dialer specification
requirements of different areas or countries.
Rev. 0.10
1 October 1, 2002

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Preliminary
HT95L100/10P
Selection Table
Part No.
Operating Program Data Normal Dialer
Voltage Memory Memory I/O I/O
LCD
Timer
HT95A200
HT95A20P
2.4V~5.5V
4K´16
1152´8
28
8
¾ 16-bit´2
HT95A300
HT95A30P
2.4V~5.5V
8K´16
2112´8
28
8
¾ 16-bit´2
HT95L100
HT95L10P
2.4V~5.5V
4K´16
1152´8 16~20
8
16´8~20´8 16-bit´2
HT95L200
HT95L20P
2.4V~5.5V
8K´16
1152´8 20~28
8
24´8~24´16 16-bit´2
HT95L300
HT95L30P
2.4V~5.5V
8K´16
2112´8 16~28
8
36´16~48´16 16-bit´2
HT95C200
HT95C20P
2.4V~5.5V
8K´16
1152´8 20~28
8
24´8~24´16 16-bit´2
HT95C300
HT95C30P
2.4V~5.5V
8K´16
2112´8 16~28
8
36´16~48´16 16-bit´2
Stack
8
8
8
8
8
8
8
External
Interrupt
4
4
4
4
4
4
4
DTMF
Generator
Ö
Ö
Ö
Ö
Ö
Ö
Ö
FSK
Receiver
¾
¾
¾
¾
¾
Ö
Ö
Package
48SSOP
48SSOP
64QFP
100QFP
100QFP
128QFP
128QFP
Note: Part numbers suffixed with ²P² are OTP devices, all others are mask version devices.
Block Diagram
RES
X1
X2
XC
H .I
H .O
HDI
HDO
HKS
PO
DNPO
XM U TE
VDD
VSS
P ow erD ow n
D e te c to r &
R e s e t C ir c u it
P ro g ra m
ROM
P ro g ra m
C o u n te r
STAC K0
STAC K1
STAC K2
STAC K3
STAC K4
STAC K5
STAC K6
STAC K7
32768H z
R TC
In te rru p t
C ir c u it
IN T C 0
IN T C 1
In s tr u c tio n
R e g is te r
M P0
M P1
M
U
D ATA
M e m o ry
X
In s tr u c tio n
D ecoder
T im in g
G e n e ra to r
M UX
A LU
A C C S h ifte r
STATU S
O S C C ir c u it 3 2 7 6 8 H z
M
W D TS
W DT O SC
S y s te m C lo c k /4
U
X
W D T P r e s c a le r
D ia le r I/O
P ow er
S u p p ly
Low
B a tte ry
D e te c to r
L C D D r iv e r
2 0 (1 6 )´ 8
TM R 1
TM R 1C
M
U
X
32768H z
TM R 0
TM R 0C
M
U
X
S y s te m c lo c k /4
IN T /T M R 1
TM R 0
P A P A 0~P A 7
PAC
P B P B 0~P B 7
PBC
P E P E 0~P E 3
PEC
D TM .
G e n e ra to r
3 .5 8 M H z
32768H z
o r 3 .5 8 M H z /4
P.D
D TM .
M U S IC
L B IN C O M 0 ~ C O M 7 S E G 0 ~ S E G 1 9 V L C D
Rev. 0.10
2 October 1, 2002

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Pin Assignment
Preliminary
HT95L100/10P
COM 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
XM U TE
DNPO
64 63 62 61 60 59 58 57 56 55 54 53 52
1 51
2 50
3 49
4 48
5 47
6 46
7 45
8 44
9 H T 9 5 L 1 0 0 /1 0 P
1 0 6 4 Q . P -A
11
43
42
41
12 40
13 39
14 38
15 37
16 36
17 35
18 34
19 33
20 21 22 23 24 25 26 27 28 29 30 31 32
SEG 6
SEG 7
SEG 8
SEG 9
S E G 10
S E G 11
S E G 12
S E G 13
S E G 14
S E G 15
S E G 1 6 /P E 0
S E G 1 7 /P E 1
S E G 1 8 /P E 2
S E G 1 9 /P E 3
V LC D
M U S IC
RES
TM R 0
D TM .
Pin Description
Pin Name
I/O
Description
CPU
VDD
¾ Positive power supply
VSS
¾ Negative power supply, ground
X1 I A 32768Hz crystal (or resonator) should be connected to this pin and X2.
X2 O A 32768Hz crystal (or resonator) should be connected to this pin and X1.
XC I External low pass filter used for frequency up conversion circuit.
RES
I Schmitt trigger reset input, active low.
INT/TMR1
Schmitt trigger input for external interrupt or Timer/Event Counter 1.
I
No internal pull-high resistor.
For INT: Edge trigger activated on a falling edge.
For TMR1: Activated on falling or rising transition edge, selected by software.
TMR0
Schmitt trigger input for Timer/Event Counter 0.
I No internal pull-high resistor.
Activated on falling or rising transition edge, selected by software.
LCD Driver
SEG0~SEG15
O LCD panel segment outputs.
SEG16~SEG19
(PE0~PE3)
O
or
I/O
LCD panel segment outputs.
SEG16~SEG19 can be nibble optioned to PE0~PE3 by software.
COM0~COM7
O LCD panel common outputs.
VLCD
I LCD driver power source.
Rev. 0.10
3 October 1, 2002

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Preliminary
HT95L100/10P
Pin Name
I/O
Description
Normal I/O
PA0~PA7
Bidirectional 8-bit input/output ports.
I/O Schmitt trigger input or CMOS output.
See mask option table for pull-high and wake-up function
PB0~PB7
Bidirectional 8-bit input/output ports.
I/O Schmitt trigger input or CMOS output.
See mask option table for pull-high function
PE0~PE3
O
or
I/O
Bidirectional 4-bit input/output ports.
Schmitt trigger input and CMOS output.
PE0~PE3 can be per nibble optioned to SEG16~SEG19 by software.
See mask option table for pull-high function
Dialer I/O (See the ²Dialer I/O function²)
Schmitt trigger input structure. An external RC network is recommended for input
HFI I debouncing.
This pin is pulled low with internal resistance of 200kW typ.
HFO
O CMOS output structure.
Schmitt trigger input structure. An external RC network is recommended for input
HDI I debouncing.
This pin is pulled high with internal resistance of 200kW typ.
HDO
O CMOS output structure.
HKS
I
This pin detects the status of the hook-switch and its combination with HFI/HDI can
control the PO pin output to make or break the line.
PO
O
CMOS output structure controlled by HKS and HFI/HDI pins and which determines
whether the dialer connects or disconnects the telephone line.
DNPO
O NMOS output structure.
XMUTE
O
NMOS output structure. Usually, XMUTE is used to mute the speech circuit when
transmitting the dialer signal.
Peripherals
DTMF
This pin outputs dual tone signals to dial out the phone number. The load resistor should
O not be less than 5kW.
MUSIC
O This pin outputs the single tone that generated by the PFD generator.
LBIN
I This pin detects battery low through external R1/R2 to determine threshold voltage.
Absolute Maximum Ratings
Supply Voltage ........................................-0.3V to 5.5V
Input Voltage .............................. VSS-0.3 to VDD+0.3V
Storage Temperature ...........................-50°C to 125°C
Operating Temperature ..........................-25°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Rev. 0.10
4 October 1, 2002

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Preliminary
HT95L100/10P
Electrical Characteristics
Ta=25°C
Symbol
CPU
Parameter
IIDL Idle Mode Current
ISLP Sleep Mode Current
IGRN
Green Mode Current
INOR
Normal Mode Current
VIL I/O Port Input Low Voltage
VIH I/O Port Input High Voltage
IOL I/O Port Sink Current
IOH I/O Port Source Current
RPH Pull-high Resistor
LBIN
Low Battery Detection
Reference Voltage
LCD Driver
VLCD
LCD Panel Power Supply
ILCD LCD Operation Current
Dialer I/O
IXMO
XMUTE Leakage Current
IOLXM
XMUTE Sink Current
IHKS HKS Input Current
RHFI
HFI Pull-low Resistance
RHDI
HDI Pull-high Resistance
IOH2 HFO Source Current
IOL2 HFO Sink Current
IOH3 HDO Source Current
IOL3 HDO Sink Current
IOH4 PO Source Current
IOL4 PO Sink Current
IOL5 DNPO Sink Current
DTMF Generator
VTDC
DTMF Output DC Level
VTOL
DTMF Sink Current
VTAC
DTMF Output AC Level
RL DTMF Output Load
ACR Column Pre-emphasis
THD
Tone Signal Distortion
Test Conditions
VDD Conditions
Min. Typ. Max. Unit
32768Hz off, 3.58MHz off,
5V CPU off, LCD off, WDT off,
no load
32768Hz on, 3.58MHz off,
5V CPU off, LCD off, WDT off,
no load
32768Hz on, 3.58MHz off,
5V CPU on, LCD off, WDT off,
no load
32768Hz on, 3.58MHz on,
5V CPU on, LCD on, WDT on,
DTMF generator off, no load
5V ¾
5V ¾
5V ¾
5V ¾
5V ¾
¾
¾
¾
¾
0
4
4
-2
10
¾2
¾ 30
¾ 50
¾3
¾1
¾5
6¾
-3 ¾
30 ¾
5V ¾
1.10 1.15 1.20
mA
mA
mA
mA
V
V
mA
mA
kW
V
¾¾
¾ VLCD=5V, 32768Hz, no load
¾
¾
35
¾ 100
V
mA
2.5V XMUTE pin=2.5V
2.5V XMUTE pin=0.5V
2.5V HKS pin=2.5V
2.5V VHFI=2.5V
2.5V VHDI=0V
2.5V VOH=2V
2.5V VOL=0.5V
2.5V VOH=2V
2.5V VOL=0.5V
2.5V VOH=2V
2.5V VOL=0.5V
2.5V VOL=0.5V
¾¾1
mA
1
¾¾
mA
¾
¾ 0.1
mA
¾ 200 ¾
kW
¾ 200 ¾
kW
-1 ¾ ¾ mA
1
¾¾
mA
-1 ¾ ¾ mA
1
¾¾
mA
-1 ¾ ¾ mA
1
¾¾
mA
1
¾¾
mA
¾¾
¾ VDTMF=0.5V
¾ Row group, RL=5kW
¾ THD£-23dB
¾ Row group=0dB
¾ RL=5kW
0.45VDD ¾ 0.7VDD V
0.1 ¾ ¾ mA
120 155 180 mVrms
5
¾¾
kW
1 2 3 dB
¾ -30 -23 dB
Rev. 0.10
5 October 1, 2002