Figure 1. X76F400 Device Operation
Load Command/Address Byte
Use of ACK Polling
The X76F400 contains a retry counter. The retry
counter allows 8 accesses with an invalid password
before any action is taken. The counter will increment
with any combination of incorrect passwords. If the
retry counter overﬂows, the memory area and both of
the passwords are cleared to “0.” If a correct password
is received prior to retry counter overﬂow, the retry
counter is reset and access is granted.
The X76F400 supports a bi-directional bus oriented
protocol. The protocol deﬁnes any device that sends
data onto the bus as a transmitter and the receiving
device as a receiver. The device controlling the transfer
is a master and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive opera-
tions. Therefore, the X76F400 will be considered a
slave in all applications.
Figure 2. Data Validity
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 2 and 3.
All commands are preceeded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F400 continuously monitors the SDA
and SCL lines for the start condition, and will not
respond to any command until this condition is met.
A start may be issued to terminate the input of a con-
trol byte or the input data to be written. This will reset
the device and leave it ready to begin a new read or
write command. Because of the push/pull output, a
start cannot be generated while the part is outputting
data. Starts are inhibited while a write is in progress.
All communications must be terminated by a stop con-
dition. The stop condition is a LOW to HIGH transition
of SDA when SCL is HIGH. The stop condition is also
used to reset the device during a command or data
input sequence, leaving the device in the standby
power mode. As with starts, stops are inhibited when
outputting data and while a write is in progress.
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8
bits. During the ninth clock cycle the receiver will pull
the SDA line LOW to acknowledge that it received the
8 bits of data.
The X76F400 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F400 will respond with an acknowl-
edge after the receipt of each subsequent 8-bit word.
REV 1.0 7/5/00
Characteristics subject to change without notice. 3 of 14