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LCZ-R00136-- 1
N o . LCY-00136
D A T E Jun.26.2001
TECHNICAL LITERATURE
FOR
Control IC for
T F T -LCD module
Model No. LZ9FC22
The technical literature is subject to change without notice.
So,please contact SHARP or its agency to start workings for
Mass production.
SHARP CORPORATION
TFT LIQUID CRYSTAL DISPLAY GROUP
Although this technical literature shows major applications of our products,
this will not guarantee the extension of industrial
prossession and other rights. And we won’t have any responsibility to your
trouble with third party over the industrial possession by using our
products.
www.DataSheet4U.com
www.DataSheet4U.com
www.DataSheet4U.com

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LCZ-R00136-- 1
1. Introduction
This data sheet is to introduce the specification of LZ9FC22 , timing Control IC for TFT - LCD module.
Applicable TFT-LCD module : QVGA(Portrate / Landscape) pixel type module
Functions: Timing Control IC for TFT-LCD module
(1)By inputting Clock signal, Horizontal sync. signal, Vertical sync. signal, the following signals
Synchronized with above signal are generated;
(A)Driving signal for source driver
:CLK,SPL,SPR,LP,PS
(B)Driving signal for gate driver
:CLS,SPS
(C)Signal for common electrode driving signal preparation :REV
(B)Signal for standard voltage preparation
:REVV0
(2)Horizontal and Vertical reverse scanning function
Input/Output signal timing chart for above cases : See Fig.1. Fig.2. Fig.3.
Outline dimensions
: See Fig.4.
2. Feature
Process
Wafer substrate
Package
Operating Temperature
Propagation delay time
: CMOS
: P-type silicon substrate
: 72QFP(0.5mm pin pitch)
: -30 ~ +85
: 1ns/gate
(Condition : VDD=3.3V, Topr=25 )
*REMARK
Not designed or rated as radiation harded

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3. Pin assignment
Pin No.
I/O
1 IC
2 ICU
3 IC
4 IC
5 IC
6 IC
7 IC
8 IC
9-
10 -
11 IC
12 IC
13 IC
14 IC
15 IC
16 IC
17 ICU
18 IC
19 IC
20 IC
21 IC
22 IC
23 IC
24 ICU
25 ICU
26 ICD
27 -
28 -
29 ICU
30 O2M
31 O2M
32 O2M
33 TO2M
34 O2M
35 TO2M
36 O2M
Signal Name
DCLK
SETR
R0
R1
R2
R3
R4
R5
GND
N.C.
G0
G1
G2
G3
G4
G5
TEST
B0
B1
B2
B3
B4
B5
TEST
HREV
ENAB
VDD
GND
TEST
REV
REVV0
PS
SPR
LBR
SPL
LP
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
I/O
O3M
-
O2M
O2M
O2M
O2M
O2M
O2M
-
-
O2M
O2M
O2M
O2M
O2M
O2M
-
O2M
O2M
O2M
O2M
O2M
O2M
-
TO2M
TO2M
-
-
TO2M
ICU
IC
IC
O2M
ICU
IC
IC
IC :Input buffer CMOS level
ICU :Input buffer CMOS level with PULL UP resistance
ICD :Input buffer CMOS level with PULL DOWN resistance
O2M :Output buffer IOL=0.8mA(VDD=3V)
TO2M :Tri-state Output buffer IOL=0.8mA(VDD=3V)
VDD :Power supply pin
GND :Earth pin
N.C. :Non Connection pin
LCZ-R00136-- 2
Signal Name
CLK
GND
OB5
OB4
OB3
OB2
OB1
OB0
VDD
GND
OG5
OG4
OG3
OG2
OG1
OG0
GND
OR5
OR4
OR3
OR2
OR1
OR0
GND
CLS
SPS
VDD
GND
UBL
VREV
TEST
SIZEC0
MOD
REM
HS
VS

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LCZ-R00136-- 3
4. Explanation of input/Output signal
Pin No. Signal Name Explanation
1 DCLK Input terminal for data clock signal
2 SETR Input terminal for control signal for PS (SIZEC0 = "L" to the apploication)
3 R0 Input terminal for red data signal(LSB)
4 R1 Input terminal for red data signal
5 R2 Input terminal for red data signal
6 R3 Input terminal for red data signal
7 R4 Input terminal for red data signal
8 R5 Input terminal for red data signal(MSB)
9 GND Ground
10 N.C. Non connection
11 G0 Input terminal for green data signal(LSB)
12 G1 Input terminal for green data signal
13 G2 Input terminal for green data signal
14 G3 Input terminal for green data signal
15 G4 Input terminal for green data signal
16 G5 Input terminal for green data signal(MSB)
17 TEST Input terminal for test normal state:H level
18 B0 Input terminal for blue data signal(LSB)
19 B1 Input terminal for blue data signal
20 B2 Input terminal for blue data signal
21 B3 Input terminal for blue data signal
22 B4 Input terminal for blue data signal
23 B5 Input terminal for blue data signal(MSB)
24 TEST Input terminal for test (normal state:H level)
25 HREV Input terminal for setting up right/left reverse scanning
H level : Normal L level : Reverse scanning
26 ENAB Input terminal for signal to settle the Horizontal display position
27 VDD Input terminal for Power Supply voltage
28 GND Input terminal for Ground
29 TEST Input terminal for test (normal state:H level)
30 REV Signal output for common electrode driving signal preparation
31 REVV0 Signal output for standard voltage preparation
32 PS Control signal output for sourve driver
33 SPR Start signal output for source driver
(for right/left reverse scannning, normally high impedance)
34 LBR Output signal for right/left reverse scannning
HREV=H : H level output
=L : L level output
35 SPL Start signal output for source driver
(for normal scanning. At right/left reverse scanning, high impedance)
36 LP Data transferring signal output for source driver
I/O
I
I
I
I
I
I
I
I
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
-
I
O
O
O
O
O
O
O

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LCZ-R00136-- 4
Pin No. Signal Name Explanation
I/O
37 CLK Clock signal output for source driver
O
38 GND Ground
-
39 OB5 Blue data signal output for source driver(MSB)
O
40 OB4 Blue data signal output for source driver
O
41 OB3 Blue data signal output for source driver
O
42 OB2 Blue data signal output for source driver
O
43 OB1 Blue data signal output for source driver
O
44 OB0 Blue data signal output for source driver(LSB)
O
45 VDD Power Supply voltage
-
46 GND Ground
-
47 OG5 Green data signal output for source driver(MSB)
O
48 OG4 Green data signal output for source driver
O
49 OG3 Green data signal output for source driver
O
50 OG2 Green data signal output for source driver
O
51 OG1 Green data signal output for source driver
O
52 OG0 Green data signal output for source driver(LSB)
O
53 GND Ground
-
54 OR5 Red data signal output for source driver(MSB)
O
55 OR4 Red data signal output for source driver
O
56 OR3 Red data signal output for source driver
O
57 OR2 Red data signal output for source driver
O
58 OR1 Red data signal output for source driver
O
59 OR0 Red data signal output for source driver(LSB)
O
60 GND Ground
-
61 CLS Clock signal output for source driver
O
62 SPS Start signal output for gate driver
O
63 VDD Power Supply voltage
-
64 GND Ground
-
65 UBL Output signal for up/down reverse scanning
VREV=H : H level output
O
VREV=L : L level outuput
66 VREV Input terminal for setting up up/down reverse scannning
(H:Normal L:Reverse scanning)
O
67 TEST Input terminal for test (normal state : L level)
I
68 SIZEC0 Input signal for drive condition change
SIZEC0 = H : Portrate QVGA(240RGB x 320)
I
= L : Landscape QVGA(320RGB x 240)
69 MOD Output signal for gate driver
O
70 REM Input terminal for reset signal (Give the signal that becomes
I
H level fixation from the L level at the time of the power supply input )
71 HS Input terminal for horizontal sync. signal
I
72 VS Input terminal for vertical sync. Signal
I