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( DataSheet : www.DataSheet4U.com )
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
256K x 36/512K x 18 Pipelined SRAM
with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between Write and
Read cycles
• Fast clock speed: 200, 166, 133, 100 MHz
• Fast access time: 3.2, 3.6, 4.2, 5.0 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 3.3V –5% and +5% power supply VCC
• Separate VCCQ for 3.3V or 2.5V I/O
• Single WEN (Read/Write) control pin
• Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
• Interleaved or linear four-word burst capability
• Individual byte Write (BWa–BWd) control (may be tied
LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
•Automatic power-down feature available using ZZ mode
or CE select
• JTAG boundary scan
• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid
Array), and 100-pin TQFP packages
Functional Description
The CY7C1354A/GVT71256ZC36 and CY7C1356A/
GVT71512ZC18 SRAMs are designed to eliminate dead
cycles when transitioning from Read to Write or vice versa.
These SRAMs are optimized for 100% bus utilization and
achieve Zero Bus Latency(ZBL)/No Bus Latency
(NoBL). They integrate 262,144 × 36 and 524,288 × 18
SRAM cells, respectively, with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. These employ high-speed, low-power CMOS
designs using advanced triple-layer polysilicon, double-layer
metal technology. Each memory cell consists of four
transistors and two high-valued resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD),
Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,
and BWd), and Read-Write Control (WEN). BWc and BWd
apply to CY7C1354A/GVT71256ZC36 only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data
occurs, either Read or Write.
A clock enable (CEN) pin allows operation of the
CY7C1354A/GVT71256ZC36/CY7C1356A/GVT71512ZC18
to be suspended as long as necessary. All synchronous inputs
are ignored when (CEN) is HIGH and the internal device
registers will hold their previous values.
There are three chip enable pins (CE, CE2, CE3) that allow the
user to deselect the device when desired. If any one of these
three are not active when ADV/LD is LOW, no new memory
operation can be initiated and any burst cycle in progress is
stopped. However, any pending data transfers (Read or Write)
will be completed. The data bus will be in high-impedance
state two cycles after chip is deselected or a Write cycle is
initiated.
The CY7C1354A/GVT71256ZC36 and CY7C1356A/
GVT71512ZC18 have an on-chip two-bit burst counter. In the
burst mode, the CY7C1354A/GVT71256ZC36 and
CY7C1356A/GVT71512ZC18 provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH)
Output Enable (OE), Sleep Enable (ZZ) and burst sequence
select (MODE) are the asynchronous signals. OE can be used
to disable the outputs at any given time. ZZ may be tied to
LOW if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Selection Guide
Maximum Access Time
Maximum Operating Current
Commercial
Maximum CMOS Standby Current Commercial
7C1354A-200
71256ZC36-5
7C1356A-200
71512ZC18-5
3.2
560
30
7C1354A-166
71256ZC36-6
7C1356A-166
71512ZC18-6
3.6
480
30
7C1354A-133 7C1354A-100
71256ZC36-7.5 71256ZC36-10
7C1356A-133 7C1356A-100
71512ZC18-7.5 71512ZC18-10
4.2 5.0
410 350
30 30
Unit
ns
mA
mA
www.DataSheet4U.com
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
wwDwo.DcautmaSehnete#t4: U3.8c-o0m5161 Rev. *B
Revised April 25, 2002

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.
Functional Block Diagram256K × 36[1]
ZZ
MODE
CCEKNE#
AADDVV//LLDD#
WRE/WN #
BBWWaa#,, BBWWbb, #
BBWWcc#,, BBWWdd#
CEC#E,,CCEE22,#C, CE3E2
Input
Registers
SA0, SCAE1N, SA
A0, A1, A
CLK
OOEE#
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Address
Control
Control Logic
Mux
Sel
Output Registers
Output Buffers
Functional Block Diagram512K × 18[1]
ZZ
MODE
CCEKNE#
AADDVV/L/LDD#
WRE/WN #
BWBaW#a,,BBWWbb#
CEC#E, ,CCEE22#, ,CCEE3 2
Input
Registers
SA0, SAC1E,NSA
A0, A1, A
CLK
OOEE#
DQa-DQd
Address
Control
Control Logic
Mux
Sel
Output Registers
Output Buffers
DQa, DQb
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
Document #: 38-05161 Rev. *B
Page 2 of 31

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Pin Configurations
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
100-lead TQFP Packages
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
VCC
VCC
VCC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1354A/
GVT71256ZC36
(256K × 36)
80 DQb
NC 1
79 DQb NC 2
78 DQb NC 3
77 VCCQ VCCQ 4
76 VSS
VSS 5
75 DQb NC 6
74 DQb NC 7
73 DQb DQb 8
72 DQb DQb 9
71
70
VSS
VSS
VDDQ VCCQ
10
11
69 DQb DQb 12
68 DQb DQb
67 VSS
VCC
66 VCC
VCC
65 VCC
VCC
64 ZZ
VSS
63 DQa DQb
13
14
15
16
17
18
62 DQa DQb 19
61 VCCQ VCCQ 20
60 VSS
VSS
21
59 DQa DQb 22
58 DQa DQb 23
57 DQa DPb 24
56 DQa NC 25
55 VSS
VSS 26
54 VCCQ VCCQ 27
53 DQa NC 28
52 DQa NC 29
51 DQa NC 30
CY7C1356A/
GVT71512ZC18
(512K × 18)
80 A
79 NC
78 NC
77 VCCQ
76 VSS
75 NC
74 DQa
73 DQa
72 DQa
71 VSS
70 VCCQ
69 DQa
68 DQa
67 VSS
66 VCC
65 VCC
64 ZZ
63 DQa
62 DQa
61 VCCQ
60 VSS
59 DQa
58 DQa
57 NC
56 NC
55 VSS
54 VCCQ
53 NC
52 NC
51 NC
Document #: 38-05161 Rev. *B
Page 3 of 31

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Pin Configurations (continued)
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
119-ball Bump BGA
CY7C1354A/GVT71256ZC36 (256K × 36)7 × 17 BGA
1234567
A VCCQ A
A NC A
A VCCQ
B NC CE2 A ADV/LD A CE3 NC
C NC A
A VCC A
A NC
D
DQc
DQc
VSS
NC
VSS
DQb
DQb
E
DQc
DQc
VSS
CE
VSS
DQb
DQb
F
VCCQ
DQc
VSS
OE
VSS
DQb
VCCQ
G
DQc
DQc
BWc
A
BWb
DQb
DQb
H
DQc
DQc
VSS
WEN
VSS
DQb
DQb
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VCCQ
DQd
VSS
CEN
VSS
DQa
VCCQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
DQd
VSS
A0
VSS
DQa
DQa
R
NC
A
MODE
VCC
VSS
A
NC
T NC NC A A A NC ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC VCCQ
CY7C1356A/GVT71512ZC18 (512K × 18)7 × 17 BGA
1234567
A VCCQ A
A NC A
A VCCQ
B NC CE2 A ADV/LD A CE3 NC
C NC A
A VCC A
A NC
D
DQb
NC
VSS
NC
VSS DQa NC
E NC DQb VSS CE VSS NC DQa
F
VCCQ
NC
VSS
OE
VSS
DQa
VCCQ
G
NC
DQb
BWb
A
VSS NC DQa
H
DQb
NC
VSS WEN VSS
DQa
NC
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K NC DQb VSS CLK VSS NC DQa
L
DQb
NC
VSS
NC
BWa
DQa
NC
M
VCCQ
DQb
VSS
CEN
VSS
NC VCCQ
N
DQb
NC
VSS
A1
VSS DQa NC
P NC DQb VSS A0 VSS NC DQa
R
NC
A
MODE
VCC
VCC
A
NC
T NC A
A NC A
A ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
Document #: 38-05161 Rev. *B
Page 4 of 31

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CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Pin Descriptions256K × 36
256K × 36
TQFP Pins
256K × 36 Pin
PBGA Pins Name
Type
Pin Description
37, 4P A0, Input- Synchronous Address Inputs: The address register is triggered by a
36, 4N A1, Synchronous combination of the rising edge of CLK, ADV/LD LOW, CEN LOW and
32, 33, 34, 35, 2A, 3A, 5A, 6A, A
true chip enables. A0 and A1 are the two least significant bits (LSBs) of
44, 45, 46, 47, 3B, 5B, 2C, 3C,
the address field and set the internal burst counter if burst cycle is
48, 49, 50, 81, 5C, 6C, 4G, 2R,
initiated.
82, 83, 99, 100 6R, 3T, 4T, 5T
93, 5L BWa, Input- Synchronous Byte Write Enables: Each nine-bit byte has its own
94, 5G BWb, Synchronous active LOW byte Write enable. On load Write cycles (when WEN and
95, 3G BWc,
ADV/LD are sampled LOW), the appropriate byte Write signal (BWx)
96 3L BWd
must be valid. The byte Write signal must also be valid on each cycle of
a burst Write. Byte Write signals are ignored when WEN is sampled
HIGH. The appropriate byte(s) of data are written into the device two
cycles later. BWa controls DQa pins; BWb controls DQb pins; BWc
controls DQc pins; BWd controls DQd pins. BWx can all be tied LOW if
always doing Writes to the entire 36-bit word.
87
4M
CEN
Input- Synchronous Clock Enable Input: When CEN is sampled HIGH, all
Synchronous other synchronous inputs, including clock are ignored and outputs
remain unchanged. The effect of CEN sampled HIGH on the device
outputs is as if the LOW-to-HIGH clock transition did not occur. For
normal operation, CEN must be sampled LOW at rising edge of clock.
88
4H
WEN
Input- Read Write: WEN signal is a synchronous input that identifies whether
Synchronous the current loaded cycle and the subsequent burst cycles initiated by
ADV/LD is a Read or Write operation. The data bus activity for the
current cycle takes place two clock cycles later.
89 4K CLK Input- Clock: This is the clock input to CY7C1354A/GVT71256ZC36. Except
Synchronous for OE, ZZ and MODE, all timing references for the device are made
with respect to the rising edge of CLK.
98, 92
4E, 6B
CE, Input- Synchronous Active LOW Chip Enable: CE and CE3 are used with
CE3 Synchronous CE2 to enable the CY7C1354A/GVT71256ZC36. CE or CE3 sampled
HIGH or CE2 sampled LOW, along with ADV/LD LOW at the rising edge
of clock, initiates a deselect cycle. The data bus will be High-Z two clock
cycles after chip deselect is initiated.
97 2B CE2 Input- Synchronous Active High Chip Enable: CE2 is used with CE and CE3
Synchronous to enable the chip. CE2 has inverted polarity but otherwise is identical
to CE and CE3.
86 4F OE Input Asynchronous Output Enable: OE must be LOW to Read data. When
OE is HIGH, the I/O pins are in high-impedance state. OE does not need
to be actively controlled for Read and Write cycles. In normal operation,
OE can be tied LOW.
85
4B
ADV/
Input- Advance/Load: ADV/LD is a synchronous input that is used to load the
LD Synchronous internal registers with new address and control signals when it is
sampled LOW at the rising edge of clock with the chip is selected. When
ADV/LD is sampled HIGH, then the internal burst counter is advanced
for any burst that was in progress. The external addresses and WEN
are ignored when ADV/LD is sampled HIGH.
31
3R
MOD
Input- Burst Mode: When MODE is HIGH or NC, the interleaved burst
E Static sequence is selected. When MODE is LOW, the linear burst sequence
is selected. MODE is a static DC input.
64 7T ZZ Input- Sleep Enable: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input has to be
either LOW or NC.
Document #: 38-05161 Rev. *B
Page 5 of 31