UM6845R / UM6845RA / UM6845RB
MPU INTERt:=ACE SIGNAL DESCRIPTION
The enable signal is the system input and is used to trigger
all data transfers between the system microprocessor and
the UM6845R. Since there is no maximum limit to the
allowable E cycle time, it Is not necessary for it to be a
continuous clock. This capability permits the UM6845R
to be easily interfaced to non-6500-compatible micro-
The R/W signal is generated by the microprocessor and is
used to control the direction of data transfers. A high on
the R/W pin allows the processor to read the data supplied
by the UM6845R; a low on the R/IN pin allows a write to
CS (Ch,jp Select)
The Chip Select input Is normally connected to the pro-
cessor address bus either directly or through a decoder.
The UM6845R is selected when CS is low.
RS (Register Select)
The Register Select input is used to access internal registers,
A low on this pin permits writes into the Address Register
and reads from the Status Register. The contents of the
Address Register is the identity of the register accessed
when RS is high.
DBo-DB? (Data Bus)
The DBo-DB? pins are the eight data lines used for
transfer of data between the processor and the UM6845R.
These lines are bl-directional and are normally high-
impedance except during read/write cycles when the chip
The DISPLAYENABLE signal is an active-high output
and is used to indicate when the UM6845R is generating
active display information. The number of horizontal
displayed characters and the number of vertical displayed
characters are both fully programmable and together are
used to generate the DISPLAY ENABLE signal.
The CU RSOR signal is an active-high output and is used
to indicate when the scan coincides with the programmed
cursor position. The cursor position may be programmed
to be any character in the address field. Furthemore,
within the character, the cursor may be programmed to
be any block of scan lines, since the start scan line and the
end scan line are both programmable.
The LPEN signal is an edge-sensitive Input and is used to
load the internal Light Pen Register with the contents of
the Refresh Scan Counter at the time the active edge
occurs. The active edge of LPEN is the low-to-high
The CCLK signal is the character timing clock input and
is used as the time base for all internal count/control
The RES Signal-is an active-low input used to initialize all
internal scan counter circuits. When RES is low, all internal
counters are stopped and cleared, all scan and video outputs
are low, and control registers are unaffected. RES must
stay low for at least one CCLK period. All scan timing is
initiated when RES goes high. In this way, RES can be
used to synchronize display frame timing with line
VIDEO INTERFACE SIGNAL DESCRIPTION
HSYNC (Horizontal Sync)
The HSYNC signal is an active-high output used to
determine the horizontal position of displayed text. It
may drive a CRT monitor directly or may be used for
composite video generation. HSYNC time position and
width are fully programmable.
VSYNC (Vertical Sync)
The VSYNC signal Is an active-high output used to
determine the vertical position of displayed text. Like
HSYNC, VSYNC may be used to drive a CRT monitor
or composite video generation circuits. VSYNC position
and width are both fully programmable.
MEMORY ADDRESS SIGNAL DESCRIPTION
MAO-MA13 (Video Display RAM Address Lines)
These signals are active-high outputs and are used to address
the Video Display RAM for character storage and display
operations. The starting scan address is fully programmable
and the ending scan address Is determined by the total
number of ch~racters displayed, which is also program-
mable, in terms of characters/line and lines/frame.
• Binary Addressing
Characters are stored in successive memory locations.
Thus, the software mus! be developed so that row
and column co-ordinates are translated to sequential-
ly-numbered addresses for video display memory