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·@)UMC
UM6845R/UM6845RA/UM6845RB
==::::====::::==::::::::::::::::CRT Conuoner
Features
• Single + 5 volt (±5%) power supply
• Alphanumeric and limited graphics capabilities
• Fully programmable display (rows, columns, blanking,
etc.)
• Interlaced or non-interlaced scan
• 50/60 Hz operation
• Fully programmable cursor
• External light pen capability
• Capable of addressing up to 16K character Video Display
RAM.
• No DMA required
• Compatible with SY6845R
• Straight-binary addressing for Video Display RAM
General Description
The UM6845R is a CRT Controller intended to provide
capability for interfacing any microprocessor family to
CRT or TV-type raster scan displays. A unique feature
is the inclusion of several modes of operation, so that the
system designer can configure the system with a wide
assortment of techniques.
Pin Configuration
GND
RES
LPEN
CCO/MAO
CC1/MA1
CC2/MA2
CC3/MA3
CC4/MA4
CC5/MA5
CC6/MA6
CC7/MA7
CRO/MA8
CR1/MA9
CR2/MA10
CR3/MA11
CR4/MA12
CR5/MA13
DISPLAY ENABLE
CURSOR
Vce
Block Diagram
VSYNC
HSYNC
RAO
RA1
RA2
RA3
RA4
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
CS
RS
E
R/W
CCLK
VCC GND
DBO-DB7
HSYNC
1 - - - - VSYNC
t---- DISPLAY ENABLE
R/!-~-+I UM6845R CRTC
CURSOR
t _ _ - - LPEN
CS ....._ _ CCLK
RS t _ _ - - RES
MAO-MA13 RAO-RA4
\{
VIDEO D.lSPLAY RAM AND CHARACTER RoM
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UM6845R / UM6845RA / UM6845R8
Absolute Maximum Ratings*
Supply Voltage, vee .............. -0.3V to + 7.0V
Input/Output Voltage, VIN ......... -0.3V to + 7.0V
Operating Temperature, Top . . . . . . . . . . . OoC to 70°C
Storage Temperature, TSTG ......... -55°C to 150°C
Notice:
All inputs contain protection circuitry to prevent damage
due. to high static discharges. Care should be exercised to
prevent unnecessary application of voltages in excess of
the allowable limits.
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. •Functional operation of
this device at these or any other conditions above those
indicated in the operation~1 sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
D.C. Electrical Characteristics
(Vee = 5.0V ± 5%, TA = 0 - 70°C, unless otherwise noted)
Symbol
VIH
VIL
liN
ITSI
VOH
VOL
Po
CIN
COUT
Characteristics
Input High Voltage
Input low Voltage
Input leakage (cp2, R/w, RES, CS, RS, lPEN, CClK)
Three-State Input leakage (DBO-DB7)
VIN = 0.4 to 2.4V
Output High Voltage
I'LOAD = -205p.A (DBO-DB7)
I LOAD = -100p.A (all others)
Output Low Voltage
ILOAD = 1.6mA
Power Dissipation
Input Capacitance
cp2, R/w, RES, CS, RS, lPEN, CClK
DBO-DB7
Output Capacitance
Min.
2.0
-0.3
-
-10.0
2.4
-
-
-
-
-
Typ.
325
Max.
Vee
0.8
2.5
+10.0
-
0.4
650
10.0
12.5
10.0
Units
V
V
p.A
p.A
V
V
mW
pF
pF
pF
TEST LOAD
Vee
UM6845R PIN
e
I
R
R = 11 Kn FOR DBo-pB7
R = 24Kn FOR ALL OTHER OUTPUTS'
e = 130pF TOTAL FOR 00-07
e = 30 pF ALL OTHER OUTPUTS
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A.C. Electrical Characteristics
MPU BUS INFERFACE CHARACTERISTICS
WRITE CYCLE
E _ _ _J
RS
CS, R/W
OATA BUS
UM6845R / UM6845RA / UM6845RB
READ CYCLE
E
RS
CS, R/Iii
OATA BUS
WRITE TIMING CHARACTERISTICS (Vcc = 5.0V ± 5%, TA = 0 - 70°C, unless otherwise noted)
Symbol
Characteristics
tCYC
Cycle Time
PWEH
E Pulse Width, High
PWEL
E Pulse Width, Low
tAS Address Set-Up Time
tAH Address Hold Time
tcs R/W, CS Set-Up Time
tCH R/W, CS Hold Time
tosw
Data Bus Set-Up Time
tOHW
Data Bus Hold Time
(tr and tf = 10 to 30 ns)
UM6845R
Min. Max.
1.0 -
440 -
420 -
80 -
0-
80 -
0-
165 -
10 -
UM6845RA
Min. Max.
0.5 -
200 -
190 -
40 -
0-
40 -
0-
60 -
10 -
UM6845RB
Min. Max.
0.33
-
150 -
140 -
30 -
0-
30 -
0-
60 -
10 -
READ TIMING CHARACTERISTICS. (Vcc = 5.0V ± 5%, TA = 0 - 70°C, unless otherwise noted)
Symbol
Characteristics
tCYC
Cycle Time
PWEH
E Pulse Width, High
PWEL
E Pulse Width, Low
tAS Address Set-Up Time
tAH Address Hold Time
tcs R/W, CS Set-Up Time
tooR
Read Access Time (Valid Data)
tOHR
Read Hold Time
tOA Data Bus Active Time (Invalid Data)
(tr and tf = 10 to 30 ns)
UM6845R
Min.
1.0
Max.
-
440 -
420 -
80 -
0-
80 -
- 290
20 60
40 -
UM6845RA
Min. Max.
0.5 -
200 -
190 -
40 -
0-
40 -
- 150
20 60
40 -
UM6845RB
Min. Max.
0.33 -
150 -
140 -
30 -
0-
30 -
- 100
20 60
40 -
Units
/-ls
ns
ns
ns
ns
ns
ns
ns
ns
Units
/-ls
ns
ns
ns
ns
ns
ns
ns
ns
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UM6845R / UM6845RA / UM6845RB
MEMORY AND VIDEO INTERFACE CHARACTERISTICS
(Vcc = 5.0V ± 5%, T A = 0 to 70°C, unless otherwise noted)
tCCH
MAO-MA13 ________________-+____-J
RAO-RA4
DISPLAY ENABLE ________________-+______-J
HSYNC, VSYNC ________________-+______--J
CURSOR ________________-+________J
Symbol
TCCH
TCCY
Tr , tt
tMAO
tRAO
tOTO
tHSD
tvso
tcoo
Parameter
Minimum Clock Pulse Width, High
Clock Frequency
Rise and Fall Time for Clock Input
Memory Address Delay Time
Raster Address Delay Time
Display Timing Delay Time
Horizontal Sync Delay Time
Vertical Sync Delay Time
Cursor Display Timing Delay Time
Min.
200
Typ.
100
100
160
160
160
160
Max.
2.5
20
160
160
300
300
300
300
Units
ns
MHz
ns
ns
ns
ns
ns
ns
ns
LIGHT PEN STROBE TIMING
NOTE:
"Safe" time position for
LPEN positive edge to
cause address n+2 to load
into Light Pen Register.
tLP2 and tLP1 are time
positions causing uncertain
results.
CCLK
LPEN~~
X"'__ X"'___ x==MAO-MA13 ___n____-J
n_+_1_ _-J
n_+_2____...
Symbol
Characteristics
tLPH
tLP1
tLP2
lPEN Strobe Width
lPEN to CClK Delay
CClK to lPEN Delay
tr and tf = 20 ns (max.)
UM6845R
Min.
Max.
100 -
- 120
-0
UM6845RA
Min.
Max.
100 -
- 120
-0
UM6845RB
Min.
Max.
100 -
- 120
-0
Unit
ns
ns
ns
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Cl)UMC
UM6845R / UM6845RA / UM6845RB
Pin Description
MPU INTERt:=ACE SIGNAL DESCRIPTION
E (Enable)
The enable signal is the system input and is used to trigger
all data transfers between the system microprocessor and
the UM6845R. Since there is no maximum limit to the
allowable E cycle time, it Is not necessary for it to be a
continuous clock. This capability permits the UM6845R
to be easily interfaced to non-6500-compatible micro-
processors.
RIW (ReacllWrite)
The R/W signal is generated by the microprocessor and is
used to control the direction of data transfers. A high on
the R/W pin allows the processor to read the data supplied
by the UM6845R; a low on the R/IN pin allows a write to
the UM6845R
CS (Ch,jp Select)
The Chip Select input Is normally connected to the pro-
cessor address bus either directly or through a decoder.
The UM6845R is selected when CS is low.
RS (Register Select)
The Register Select input is used to access internal registers,
A low on this pin permits writes into the Address Register
and reads from the Status Register. The contents of the
Address Register is the identity of the register accessed
when RS is high.
DBo-DB? (Data Bus)
The DBo-DB? pins are the eight data lines used for
transfer of data between the processor and the UM6845R.
These lines are bl-directional and are normally high-
impedance except during read/write cycles when the chip
is selected.
DISPLAY ENABLE
The DISPLAYENABLE signal is an active-high output
and is used to indicate when the UM6845R is generating
active display information. The number of horizontal
displayed characters and the number of vertical displayed
characters are both fully programmable and together are
used to generate the DISPLAY ENABLE signal.
CURSOR
The CU RSOR signal is an active-high output and is used
to indicate when the scan coincides with the programmed
cursor position. The cursor position may be programmed
to be any character in the address field. Furthemore,
within the character, the cursor may be programmed to
be any block of scan lines, since the start scan line and the
end scan line are both programmable.
LPEN
The LPEN signal is an edge-sensitive Input and is used to
load the internal Light Pen Register with the contents of
the Refresh Scan Counter at the time the active edge
occurs. The active edge of LPEN is the low-to-high
transition.
CCLK
The CCLK signal is the character timing clock input and
is used as the time base for all internal count/control
functions.
RES
The RES Signal-is an active-low input used to initialize all
internal scan counter circuits. When RES is low, all internal
counters are stopped and cleared, all scan and video outputs
are low, and control registers are unaffected. RES must
stay low for at least one CCLK period. All scan timing is
initiated when RES goes high. In this way, RES can be
used to synchronize display frame timing with line
frequency.
VIDEO INTERFACE SIGNAL DESCRIPTION
HSYNC (Horizontal Sync)
The HSYNC signal is an active-high output used to
determine the horizontal position of displayed text. It
may drive a CRT monitor directly or may be used for
composite video generation. HSYNC time position and
width are fully programmable.
VSYNC (Vertical Sync)
The VSYNC signal Is an active-high output used to
determine the vertical position of displayed text. Like
HSYNC, VSYNC may be used to drive a CRT monitor
or composite video generation circuits. VSYNC position
and width are both fully programmable.
MEMORY ADDRESS SIGNAL DESCRIPTION
MAO-MA13 (Video Display RAM Address Lines)
These signals are active-high outputs and are used to address
the Video Display RAM for character storage and display
operations. The starting scan address is fully programmable
and the ending scan address Is determined by the total
number of ch~racters displayed, which is also program-
mable, in terms of characters/line and lines/frame.
• Binary Addressing
Characters are stored in successive memory locations.
Thus, the software mus! be developed so that row
and column co-ordinates are translated to sequential-
ly-numbered addresses for video display memory
operations.
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