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®
ISL6310
Data Sheet
October 19, 2005
FN9209.2
Two-Phase Buck PWM Controller with
High Current Integrated MOSFET Drivers
The ISL6310 is a two-phase PWM control IC with integrated
MOSFET drivers. It provides a precision voltage regulation
system for multiple applications including, but not limited to,
high current low voltage point-of-load converters, embedded
applications and other general purpose low voltage medium
to high current applications. The integration of power
MOSFET drivers into the controller IC marks a departure
from the separate PWM controller and driver configuration of
previous multi-phase product families. By reducing the
number of external parts, this integration allows for a cost
and space saving power management solution.
Output voltage can be programmed using the on-chip DAC
or an external precision reference. A two bit code programs
the DAC reference to one of 4 possible values (0.6V, 0.9V,
1.2V and 1.5V). A unity gain, differential amplifier is provided
for remote voltage sensing, compensating for any potential
difference between remote and local grounds. The output
voltage can also be offset through the use of single external
resistor. An optional droop function is also implemented and
can be disabled for applications having less stringent output
voltage variation requirements or experiencing less severe
step loads.
A unique feature of the ISL6310 is the combined use of both
DCR and rDS(ON) current sensing. Load line voltage
positioning and overcurrent protection are accomplished
through continuous inductor DCR current sensing, while
rDS(ON) current sensing is used for accurate channel-current
balance. Using both methods of current sampling utilizes the
best advantages of each technique.
Protection features of this controller IC include a set of
sophisticated overvoltage and overcurrent protection.
Overvoltage results in the converter turning the lower
MOSFETs ON to clamp the rising output voltage and protect
the load. An OVP output is also provided to drive an optional
crowbar device. The overcurrent protection level is set
through a single external resistor. Other protection features
include protection against an open circuit on the remote
sensing inputs. Combined, these features provide advanced
protection for the output load.
Features
• Integrated Multi-Phase Power Conversion
- 1 or 2 Phase Operation
• Precision Output Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.8% System Accuracy Over Temperature
(for REF=0.6V and 0.9V)
- ±0.5% System Accuracy Over Temperature
(for REF=1.2V and 1.5V)
- Usable for output voltages not exceeding 2.3V
- Adjustable Reference-Voltage Offset
• Precision Channel Current Sharing
- Uses Loss-Less rDS(ON) Current Sampling
• Optional Load Line (Droop) Programming
- Uses Loss-Less Inductor DCR Current Sampling
• Variable Gate-Drive Bias - 5V to 12V
• Internal or External Reference Voltage Setting
- On-Chip Adjustable Fixed DAC Reference voltage with
2-bit Logic Input Selects from Four Fixed Reference
Voltages (0.6V, 0.9V, 1.2V, 1.5V)
- Reference can be Changed Dynamically
- Can use an External Voltage Reference
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
- OVP Pin to Drive Optional Crowbar Device
• Selectable Operation Frequency up to 1.5MHz per phase
• Digital Soft-Start
• Capable of Start-up in a Pre-Biased Load
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• High Current DDR/Chipset core voltage regulators
• High Current, Low voltage DC/DC converters
• High Current, Low voltage FPGA/ASIC DC/DC converters
Ordering Information
PART NUMBER*
PART MARKING
TEMPERATURE (°C)
PACKAGE
PKG. DWG. #
ISL6310CRZ (Note)
ISL6310CRZ
0 to 70
32 Ld 5x5 QFN (Pb-free)
L32.5x5
ISL6310IRZ (Note)
ISL6310IRZ
-40 to 85
32 Ld 5x5 QFN (Pb-free)
L32.5x5
ISL6310EVAL1
Evaluation Platform
* Awddw“-Tw” s.Duffiax tfoar Stapheeanedtr4eeUl. .com
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinout
ISL6310
ISL6310 (QFN)
TOP VIEW
32 31 30 29 28 27 26 25
REF 1
24 BOOT1
OFST 2
23 PHASE1
VCC 3
22 OVP
COMP 4
FB 5
33
GND
21 REF1
20 ENLL
VDIFF 6
19 PHASE2
RGND 7
18 BOOT2
VSEN 8
17 UGATE2
9 10 11 12 13 14 15 16
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FN9209.2
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Block Diagram
ICOMP DROOP OCSET
ISL6310
PGOOD OVP
ISUM
IREF
ISEN AMP
100µA
OC
RGND
VSEN
VDIFF
x1
x1
UVP
OVP
OVP
+150mV
x 0.82
+1V
SOFT-START
AND
FAULT LOGIC
0.2V
CLOCK AND
SAWTOOTH
GENERATOR
PWM1
REF1
REF0
DAC
DAC
PWM2
REF
FB
COMP
OFST
OFFSET
E/A
CHANNEL
CURRENT
BALANCE
CHANNEL
CURRENT
SENSE
1
N
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ISEN1
ISEN2
ENLL
0.66V
POWER-ON
RESET
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
PHASE 2
DETECT
GND
3
VCC
PVCC
BOOT1
UGATE1
PHASE1
LGATE1
FS
BOOT2
UGATE2
PHASE2
LGATE2
2PH
FN9209.2
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Typical Application - ISL6310
ISL6310
VDIFF
FB
COMP
PVCC
VSEN
RGND
+5V 2PH
VCC
BOOT1
UGATE1
PHASE1
ISEN1
LGATE1
OFST
FS
DAC
REF
ISL6310
+12V
REF1
REF0
OVP
PGOOD
GND
ENLL
IREF
DROOP
OCSET ICOMP
BOOT2
UGATE2
PHASE2
ISEN2
ISUM
LGATE2
+12V
+12V
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LOAD
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ISL6310
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
Absolute Boot Voltage, VBOOT . . . . . . . . GND - 0.3V to GND + 36V
Phase Voltage, VPHASE . . . . . . . . GND - 0.3V to 15V (PVCC = 12)
GND - 8V (<400ns, 20µJ) to 24V (<200ns, VBOOT-PHASE = 12V)
Upper Gate Voltage, VUGATE . . . . VPHASE - 0.3V to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
Lower Gate Voltage, VLGATE. . . . . . . . GND - 0.3V to PVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
QFN Package (Notes 1, 2) . . . . . . . . . .
35
5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Recommended Operating Conditions
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%
Ambient Temperature (ISL6310CR, ISL6310CRZ) . . . . 0°C to 70°C
Ambient Temperature (ISL6310IR, ISL6310IRZ) . . . .-40°C to 85°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
BIAS SUPPLY AND INTERNAL OSCILLATOR
Input Bias Supply Current
Gate Drive Bias Current
IVCC; ENLL = high
IPVCC; ENLL = high, all gate outputs open,
Fsw = 250kHz
VCC POR (Power-On Reset) Threshold
VCC Rising
VCC Falling
PVCC POR (Power-On Reset) Threshold
PVCC Rising
PVCC Falling
Oscillator Ramp Amplitude (Note 3)
Maximum Duty Cycle (Note 3)
VPP
CONTROL THRESHOLDS
ENLL Rising Threshold
ENLL Hysteresis
COMP Shutdown Threshold
COMP Falling
REFERENCE AND DAC
System Accuracy (DAC = 0.6V, 0.9V)
DROOP connected to IREF
System Accuracy (DAC = 1.2V, 1.50V)
DROOP connected to IREF
DAC Input Low Voltage (REF0, REF1)
DAC Input High Voltage (REF0, REF1)
External Reference (Note 3)
OFS Sink Current Accuracy (Negative Offset)
OwFSwSowur.cDe CautrareSnt hAcecuerat4cyU(P.ocsiotivme Offset)
ROFS = 30kfrom OFS to VCC
ROFS = 10kfrom OFS to GND
MIN TYP MAX UNITS
- 15 20 mA
- 1.5 3.0 mA
4.25 4.38 4.50 V
3.75 3.88 4.00 V
4.25 4.38 4.50 V
3.75 3.88 4.00 V
- 1.50 - V
- 66.6 - %
- 0.66
- 100
0.25 0.35
-V
- mV
0.5 V
-0.8 -
0.8 %
-0.5 -
0.5 %
- - 0.4 V
0.8 -
-V
0.6 - 1.75 V
47.5 50.0 52.5 µA
47.5 50.0 52.5 µA
5 FN9209.2
October 19, 2005